Signal receiver with multi-level sampling

1. A method, comprising:

in an electronic device:

sampling in a first level, at a particular main sampling rate, an input signal;

sampling in a second level output of said first level, at a second sampling rate that is reduced compared to said main sampling rate; and

processing in a third level output of said second level, wherein the processing in said third level comprises:

sampling at a third sampling rate that is reduced compared to said second sampling rate; and

applying analog-to-digital conversion.

2. The method according to claim 1 , comprising applying low-noise amplification to said input signal in said first level.

3. The method according to claim 1 , comprising setting said second sampling rate and/or said third sampling rate by configuring clock signals used in said second level and/or said third level, based on a clock signal applied in said first level.

4. The method according to claim 3 , comprising reducing a frequency of each clock signal used in said second level relative to a frequency of said clock signal applied in said first level.

5. The method according to claim 4 , comprising reducing a frequency of each clock signal used in said third level relative to a frequency of a corresponding clock signal used in said second level.

6. The method according to claim 1 , comprising holding output signals of each of said first level, said second level, and said third level, during non-read periods as determined based on an applicable sampling rate.

7. The method according to claim 6 , comprising holding said output signals using grounding logic.

8. A system, comprising:

one or more circuits for use in an electronic device, the one or more circuits being operable to:

sample in a first level, at a particular main sampling rate, an input signal;

sample in a second level output of said first level, at a second sampling rate that is reduced compared to said main sampling rate; and

process in a third level, output of said second level, wherein the processing in the third level comprises:

sampling at a third sampling rate that is reduced compared to said second sampling rate; and

applying analog-to-digital conversion.

9. The system according to claim 8 , wherein said one or more circuits are operable to apply low-noise amplification to said input signal in said first level.

10. The system according to claim 8 , wherein said one or more circuits are operable to set said second sampling rate and/or said third sampling rate by configuring clock signals used in said second level and/or said third level, based on a clock signal applied in said first level.

11. The system according to claim 10 , wherein said one or more circuits are operable to reduce a frequency of each clock signal used in said second level relative to a frequency of said clock signal applied in said first level.

12. The system according to claim 11 , wherein said one or more circuits are operable to reduce frequency of each clock signal used in said third level relative to a frequency of a corresponding clock signal used in said second level.

13. The system according to claim 8 , wherein said one or more circuits are operable to hold output signals of each of said first level, said second level, and said third level, during non-read periods as determined based on an applicable sampling rate.

14. The system according to claim 13 , wherein said one or more circuits are operable to hold said output signals based on grounding logic.

15. A system, comprising:

a signal receiver implemented on a single chip, the signal receiver comprising:

first sampling circuitry that is operable to sample in a first level, an input signal, at a particular main sampling rate;

second sampling circuitry that is operable to sample in a second level, output of said first sampling circuitry, at a second sampling rate that is reduced compared to said main sampling rate; and

third sampling circuitry that is operable to sample in a third level, one or more outputs of said second sampling circuitry, at a third sampling rate that is reduced compared to said second sampling rate; and

analog-to-digital conversion circuitry that is operable to apply analog-to-digital conversion to one or more outputs of said third sampling circuitry.

16. The system according to claim 15 , wherein said signal receiver comprises a low-noise amplifier for amplifying said input signal in said first level.

17. The system according to claim 15 , wherein said signal receiver comprises a buffer for buffering said output of said first sampling circuitry, and/or one or more second-level buffers each of which is operable to buffer a corresponding output in said second sampling circuitry.

18. The system according to claim 15 , wherein said signal receiver is operable to set said second sampling rate and/or said third sampling rate by configuring clock signals used in said second sampling circuitry and/or said third sampling circuitry, based on a clock signal driving said first sampling circuitry.

19. The system according to claim 18 , wherein said signal receiver is operable to:

reduce, relative to frequency of said clock signal driving said first sampling circuitry, frequency of each clock signal used in said second sampling circuitry; and

reduce frequency of each clock signal used in said third sampling circuitry, relative to frequency of a corresponding clock signal used in said second sampling circuitry.

20. The system according to claim 15 , wherein said signal receiver is operable to perform at least some of digital processing of one or more outputs of said analog-to-digital conversion circuitry, said digital processing comprising filtering and decoding to extract desired signals or data.