Apparatus and method for transferring multiple asynchronous clock signals over a single conductor
View Patent ↗Methods and systems for transferring two clock signals over a single conductor are disclosed. According to various disclosed embodiments, first and second input clock signals are generated at a first module. The rising and falling edges of a generated reference clock signal are used to transfer the two clock signals from the first module to a second module over the single conductor.
1. An apparatus, comprising:
first and second clocks operable to generate first and second input clock signals, respectively, wherein the first and second input clock signals are asynchronous in relation to one another;
a first edge detector configured to receive the first input clock signal, the first edge detector operable to detect a rising edge of the first input clock signal and to generate a first enable signal;
a second edge detector configured to receive the second input clock signal, the second edge detector operable to detect the rising edge of the second input clock signal and to generate a second enable signal;
a first divider configured to receive the first enable signal and operable to generate a first adjusted enable signal based on a first predetermined factor; and
a dual clock generator configured to receive the first adjusted enable signal and the second enable signal, and in response operable to generate a reference clock signal and transmit the reference clock signal over a single conductor.
2. The apparatus of claim 1 , wherein the second clock signal is a free-run clock or a second network clock.
3. The apparatus of claim 1 , wherein the apparatus is a central processor unit (CPU) module.
4. The apparatus of claim 1 , wherein the frequency of the first adjusted enable signal is approximately equal to the frequency of the second enable signal.
5. The apparatus of claim 1 , wherein the first divider is configured to insert a guard time between the first and second enable signals to prevent overlap of the first and second enable signals.
6. An apparatus comprising:
a first edge detector configured to receive a reference clock signal via a single conductor, the first edge detector operable to detect a rising edge of the reference clock signal and to generate a first enable signal;
a second edge detector configured to receive the reference clock signal via the single conductor, the second edge detector operable to detect a falling edge of the reference clock signal and to generate a second enable signal;
a first controlled oscillator configured to receive the first enable signal and operable to track the first enable signal to generate a first output clock signal;
an integer controlled oscillator configured to receive the second enable signal and operable to generate a third enable signal that compensates the rate of the second enable signal; and
a second controlled oscillator configured to receive the third enable signal and operable to track the third enable signal to generate a second output clock signal.
7. The apparatus of claim 6 , wherein the apparatus is a peripheral module.
8. The apparatus of claim 7 , wherein the peripheral module is connected to a CPU module via the single conductor.
9. The apparatus of claim 8 , wherein the reference clock signal is transmitted by a CPU module over the single conductor.
10. A method for transferring two asynchronous clock signals over a single conductor, comprising:
generating, at a first module, first and second input clock signals;
detecting, at the first module, a rising edge of the first input clock signal, and in response generating a first enable signal;
detecting, at the first module, a rising edge of the second input clock signal, and in response generating a second enable signal;
inserting a guard time between the first and the second enable signals to prevent overlap of the first and the second enable signals;
generating, at the first module, a reference clock signal responsive to the first and second enable signals, wherein the reference clock signal is representative of the first and second input clock signals;
receiving, by a second module over the single conductor, the reference clock signal;
detecting, at the second module, rising and falling edges of the reference clock signal, and in response generating third and fourth enable signals, respectively;
generating, at the second module, a first output clock signal by sampling the third enable signal;
generating, at the second module, a fifth enable signal that compensates the rate of the fourth enable signal;
generating, at the second module, a second sampled output clock signal by sampling the fifth enable signal.
11. The method of claim 10 , wherein the first and second output clock signals are synchronized with the first and the second input clock signals, respectively.
12. The method of claim 10 , wherein the first input clock signal is synchronized with a network clock.
13. The method of claim 10 , wherein the second input clock signal is a free-run clock or a second network clock.
14. The method of claim 10 , wherein the first module is a central processor unit (CPU) module.
15. The method of claim 10 , wherein the second module is a peripheral module.
16. The method of claim 10 , wherein the first and second input clock signals are asynchronous in relation to one another.
17. The method of claim 10 , wherein the guard time is inserted by a counter.
18. The method of claim 10 , wherein the guard time is inserted by a divider.