METHODS AND APPARATUS FOR ERROR CODING

1 . A method of implementing a low-density parity-check code comprising:

receiving data;

for a plurality of vectors in a coding matrix associated with the low-density parity-check code:

retrieving, from one or more interleavers, one or more addresses;

using said one or more retrieved address to retrieve one or more symbols from said data; and

performing a parity-check operation corresponding to a particular said vector using said one or more symbols retrieved from said data,

wherein each of the performed parity-check operations are used to implement the low-density parity-check code.

2 . A method according to claim 1 , wherein, for a particular vector of the coding matrix, retrieving, from one or more interleavers, one or more addresses comprises:

determining a first address corresponding to the particular vector; and

retrieving, from a plurality of interleavers, a plurality of second addresses using the first address.

3 . A method according to claim 2 , wherein the number of interleavers contribute to a weight of at least one vector in the coding matrix.

4 . A method according to claim wherein, for each first address, a distinct second address is retrieved from each of the plurality of interleavers.

5 . A method according to claim 1 , wherein, for at least one vector of the coding matrix, retrieving, from one or more interleavers, one or more addresses comprises:

determining a one or more first addresses corresponding to the at least one vector; and

retrieving, from a first interleaver, a respective first set of one or more second addresses using the one or more first addresses.

6 . A method according to claim 5 , wherein a range for the respective plurality of second addresses contributes to a vector weight of the coding matrix.

7 . A method according to claim 5 , wherein, for at least one vector of the coding matrix, retrieving, from one or more interleavers, one or more addresses comprises:

retrieving from a second interleaver a respective second set of one or more second addresses.

8 . A method according to claim 1 , wherein each interleaver has a length that is proportional to a dimension of the coding matrix.

9 . A method according to claim 1 , wherein at least one interleaver comprises a permutation polynomial interleaver.

10 . A method according to claim 9 , wherein a permutation polynomial interleaver comprises a quadratic permutation polynomial interleaver.

11 . A method according to claim 1 , wherein the coding matrix comprises one of: a low-density parity-check matrix H in a non-systematic form, wherein a vector comprises a row of said matrix; a low-density parity-check matrix H′ in a systematic form, wherein a vector comprises a row of said matrix; a generator matrix G, wherein a vector comprises a column of said matrix.

12 . A method according to claim 1 , wherein the data comprises a data vector to be encoded, performing a parity-check operation comprises determining a parity-check symbol and the method comprises:

generating an encoded block using the data to be encoded and each of said determined parity-check symbols.

13 . A method according to claim 1 , wherein the data comprises a code vector received over a noisy communication channel and performing a parity-check operation comprises:

implementing a functional node in a decoding process using said one or more symbols retrieved from said data, the decoding process being used to determine data that was sent over the communication channel.

14 . A method according to claim 1 , wherein a symbol comprises a bit value.

15 . An apparatus for implementing a low-density parity-check code comprising:

at least one memory arranged to store data;

one or more interleavers, an interleaver being arranged to implement a mapping between a first address and a second address, a first address being associated with a particular vector in a coding matrix associated with the low-density parity-check code and a second address corresponding to a particular symbol of the data as stored in the memory;

a coding component arranged to, for a plurality of vectors in the coding matrix, use one or more second addresses from the one or more interleavers to retrieve one or more symbols of the data stored in memory,

the coding component being further arranged to perform at least a plurality of parity check operations, a parity check operation corresponding to a vector in the coding matrix and being performed using said retrieved one or more symbols of the data, the plurality of parity check operations being used to implement the low-density parity-check code.

16 . The apparatus according to claim 15 , comprising:

a plurality of interleavers arranged to determine a respective plurality of second addresses based on at least one first address,

wherein the coding component is arranged to use said plurality of second addresses to retrieve a plurality of symbols from the memory and perform a parity-check operation accordingly using said retrieved plurality of symbols.

17 . (canceled)

18 . The apparatus according to claim 16 , wherein the number of interleavers in said plurality of interleavers is dependent on at least one vector weight of the coding matrix.

19 . (canceled)

20 . The apparatus according to claim 16 , wherein each interleaver is arranged to map a first range of first addresses onto a second range of second addresses, at least one of the first and second ranges being proportional to a dimension of the coding matrix.

21 - 25 . (canceled)

26 . The apparatus according to claim 15 , wherein the coding component comprises an encoder arranged to calculate a parity-check symbol in a parity check operation and the data comprises a data vector to be encoded.

27 - 36 . (canceled)

37 . A method of configuring one or more interleavers for use in implementing a low-density parity-check code comprising:

selecting a coding matrix associated with the low-density parity-check code; and

determining one or more interleaver parameters that implement a mapping for one or more interleavers from a first address corresponding to a vector in the coding matrix to a second address corresponding to a symbol position in data to be encoded or decoded, the mapping being selected from a plurality of potential mappings based on one or more error coding criteria.