Electronic device
View Patent ↗In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
1. An electronic device comprising:
a substrate having a first main surface, a second main surface opposite the first main surface and a plurality of wirings;
a first semiconductor chip arranged above the first main surface and having a first obverse surface, a CPU circuit and a plurality of bumps formed on the first obverse surface;
a first memory chip having a first group of electrodes; and
a second memory chip having a second group of electrodes and through electrodes penetrating the second memory chip in a thickness direction of the second memory chip, the through electrodes being electrically connected to the second group of electrodes;
wherein the first memory chip is stacked on the second memory chip over the substrate such that the first group of electrodes of the first memory chip are electrically connected to the through electrodes of the second memory chip,
wherein the first group of electrodes of the first memory chip, the second groups of electrodes of the second memory chips are arranged in a first predetermined pitch, and
wherein the bumps of the first semiconductor chip, the second groups of electrodes of the second memory chips are electrically connected to the wirings of the substrate.
2. The electronic device according to claim 1 ,
wherein the first group of electrodes is arrayed in a substantially central area of the first memory chip in a cross section view, and
wherein the second group of electrodes, the through electrodes are arrayed in the substantially central area of the second memory chip in a cross section view.
3. The electronic device according to claim 1 ,
wherein the substrate includes a plurality of external electrodes, and
wherein the external electrodes are electrically connected the bumps of the first semiconductor chip via the wirings of the substrate.
4. The electronic device according to claim 1 ,
wherein the first semiconductor chip and the substrate are connected by flip-chip connection.
5. The electronic device according to claim 1 ,
wherein the second memory chip and the substrate are connected by flip-chip connection.