Time-to-digital convertor-assisted phase-locked loop spur mitigation
View Patent ↗Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.
1. A circuit that compensates for an undesired fractional spur in a baseband signal due to a fractional phase lock loop (PLL), the circuit comprising:
a time-to-digital converter (TDC) configured to determine a phase difference between a reference frequency received by the fractional PLL and an output oscillating signal generated by the fractional PLL, the output oscillating signal including an output frequency and the undesired fractional spur, the output oscillating signal used to convert a first signal to the baseband signal;
a digital signal processor (DSP) configured to estimate an amplitude and a phase of the undesired fractional spur based on the determined phase difference, and to construct an estimate of the fractional spur; and
combination logic configured to apply the constructed estimate of the fractional spur to the baseband signal to generate a compensated baseband signal.
2. The circuit of claim 1 , wherein the combination logic comprises a multiplier configured to multiply the baseband signal by the constructed estimate of the fractional spur subtracted from one to generate the compensated baseband signal.
3. The circuit of claim 1 , wherein the combination logic comprises a divider configured to divide the baseband signal by the constructed estimate of the fractional spur added to one to generate the compensated baseband signal.
4. The circuit of claim 1 , wherein the fractional PLL is an analog fractional PLL and the TDC is an analog TDC.
5. The circuit of claim 1 , where the TDC comprises:
first logic configured to determine a rising edge of the output oscillating signal;
second logic configured to determine a first rising edge of the reference frequency that is subsequent to the determined rising edge of the output oscillating signal; and
third logic configured to determine a difference between the determined rising edge of the output oscillating signal and the determined first rising edge of the reference frequency, the difference being the phase difference.
6. The circuit of claim 1 , wherein the constructed estimate of the fractional spur is applied to an analog version of the baseband signal.
7. The circuit of claim 1 , wherein the constructed estimate of the fractional spur is applied to a digital version of the baseband signal.
8. A method for compensating for an undesired fractional spur in a baseband signal due to a fractional phase lock loop (PLL), the method comprising:
determining a phase difference between a reference frequency received by the fractional PLL and an output oscillating signal generated by the fractional PLL, wherein the output oscillating signal includes an output frequency and the undesired fraction spur, and the output oscillating signal is used to convert a first signal to the baseband signal;
estimating an amplitude and a phase of the undesired fractional spur based on the determined phase difference;
constructing an estimate of the fractional spur based on the estimated amplitude and phase of the undesired fractional spur;
applying the constructed estimate of the fractional spur to the baseband signal to generate a compensated baseband signal.
9. The method of claim 8 , wherein said applying comprises:
multiplying the baseband signal by the constructed estimate of the fractional spur subtracted from one to generate the compensated baseband signal.
10. The method of claim 8 , further comprising:
dividing the baseband signal by the constructed estimate of the fractional spur added to one to generate the compensated baseband signal.
11. The method of claim 8 , wherein the fractional PLL is an analog fractional PLL.
12. The circuit of claim 8 , where determining the phase difference between the reference frequency and the output oscillating signal comprises:
determining a rising edge of the output oscillating signal;
determining a first rising edge of the reference frequency that is subsequent to the determined rising edge of the output oscillating signal; and
determining a difference between the determined rising edge of the output oscillating signal and the determined first rising edge of the reference frequency, the difference being the phase difference.
13. The circuit of claim 8 , wherein applying the constructed estimate of the fractional spur to the baseband signal to generate a compensated baseband signal comprises applying the constructed estimate of the fractional spur to an analog version of the baseband signal.
14. The circuit of claim 8 , wherein applying the constructed estimate of the fractional spur to the baseband signal to generate a compensated baseband signal comprises applying the constructed estimate of the fractional spur to a digital version of the baseband signal.
15. A circuit that compensates for an undesired fractional spur in a first signal due to a fractional phase lock loop (PLL), the circuit comprising:
a time-to-digital converter (TDC) configured to determine a phase difference between a reference frequency received by the fractional PLL and an output oscillating signal generated by the fractional PLL, the output oscillating signal including an output frequency and the undesired fractional spur, the output oscillating signal used to convert a baseband signal to the first signal;
a digital signal processor (DSP) configured to estimate an amplitude and a phase of the undesired fractional spur based on the determined phase difference, and to construct an estimate of the fractional spur; and
combination logic configured to apply the constructed estimate of the fractional spur to the baseband signal to generate a compensated first signal.
16. The circuit of claim 15 , further comprising:
second combination logic configured to apply the constructed estimate to the baseband signal to generate a pre-compensated baseband signal; and
mixer logic configured to up-convert the pre-compensated baseband signal based on the output oscillating signal to generate the compensated first signal.
17. The circuit of claim 15 , wherein the fractional PLL is an analog fractional PLL and the TDC is an analog TDC.
18. The circuit of claim 15 , where the TDC comprises:
first logic configured to determine a rising edge of the output oscillating signal;
second logic configured to determine a first rising edge of the reference frequency that is subsequent to the determined rising edge of the output oscillating signal; and
third logic configured to determine a difference between the determined rising edge of the output oscillating signal and the determined first rising edge of the reference frequency, the difference being the phase difference.
19. The circuit of claim 15 , wherein the constructed estimate of the fractional spur is applied to an analog version of the baseband signal.
20. The circuit of claim 15 , wherein the constructed estimate of the fractional spur is applied to a digital version of the baseband signal.