IP Library Granted Patent US 8,921,200
Granted Patent B2
US 8,921,200 · App. 14/110,163 · Granted Dec 30, 2014

Nonvolatile storage element and method of manufacturing thereof

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Quick Facts
Patent No.
US 8,921,200
App. No.
14/110,163
Granted
Dec 30, 2014
Kind
B2
Abstract

A method of manufacturing a variable resistance nonvolatile memory element includes: forming a lower electrode layer above a substrate; forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide; forming an upper electrode layer on the variable resistance layer; and forming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask. In the etching, at least the variable resistance layer is etched using an etching gas containing bromine.

Claims (31)

1. A method of manufacturing a nonvolatile memory element, the method comprising:

forming a lower electrode layer above a substrate;

forming, on the lower electrode layer, a variable resistance layer including an oxygen-deficient transition metal oxide;

forming an upper electrode layer on the variable resistance layer; and

forming a patterned mask on the upper electrode layer and etching the upper electrode layer, the variable resistance layer, and the lower electrode layer using the patterned mask,

wherein, in the etching, at least the variable resistance layer and the lower electrode layer are etched using an etching gas containing bromine,

wherein, in the forming of the variable resistance layer, the variable resistance layer is formed to comprise a transition metal oxide having resistance which is variable according to an oxygen amount in the transition metal oxide, the resistance being increased by incorporation of an impurity in the variable resistance layer.

2. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the etching, the etching gas contains hydrogen bromide.

3. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the forming of the variable resistance layer, the impurity incorporated in the variable resistance layer is fluorine.

4. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the etching, the etching gas further comprises fluorine.

5. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the etching,

a bromine compound is attached at least to an etched end face of the variable resistance layer while the variable resistance layer is being etched.

6. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein the forming of the variable resistance layer includes:

forming, on the lower electrode layer, a first variable resistance layer comprising a transition metal oxide; and

forming, on the first variable resistance layer, a second variable resistance layer comprising a transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first variable resistance layer.

7. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the forming of the variable resistance layer,

the variable resistance layer is formed to comprise a transition metal oxide having resistance which increases with a decrease in a degree of oxygen deficiency of the variable resistance layer.

8. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the forming of the variable resistance layer,

the variable resistance layer is formed to comprise a metal oxide which is a tantalum oxide expressed as TaO x where 0<x<2.5.

9. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the forming of the upper electrode layer,

the upper electrode layer is formed to comprise one of platinum, iridium, and palladium.

10. The method of manufacturing a nonvolatile memory element according to claim 1 ,

wherein, in the etching, the upper electrode layer, the variable resistance layer, and the lower electrode layer are etched using the etching gas containing bromine.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2013
From: KAWASHIMA, YOSHIO; MIKAWA, TAKUMI; IMAI, SHINICHI
To: PANASONIC CORPORATION
Reel/Frame 031718/0182 →