IP Library › Granted Patent US 9,077,380
Granted Patent B2
US 9,077,380 · App. 14/111,045 · Granted Jul 7, 2015

Data processing device and data processing method

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Quick Facts
Patent No.
US 9,077,380
App. No.
14/111,045
Granted
Jul 7, 2015
Kind
B2
Abstract

The present technology relates to a data processing device and a data processing method that enable tolerance against error of data to be improved. In the case in which an LDPC code having a code length of DVB-S.2 of 16200 bits and an encoding rate of 1/3 is modulated by 16 QAM, if a code bit of 4×2 bits and a (i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y6, y0, y3, y4, y5, y2, y1, and y7, respectively. The present invention can be applied to a transmission system transmitting an LDPC code or the like.

Claims (196)

1. A data processing device comprising:

an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 1/3, based on a parity check matrix of an LDPC code; and

an interchanging unit that interchanges code bits of the encoded LDPC code with symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM,

wherein the encoded LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table,

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912

8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575

3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291

2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420

6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306

1505 5682 7778

7172 6830 6623

7281 3941 3505

10270 8669 914

3622 7563 9388

9930 5058 4554

4844 9609 2707

6883 3237 1714

4768 3878 10017

10127 3334 8267, and

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging unit sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, and b7 with bits y6, y0, y3, y4, y5, y2, y1, and y7, respectively.

2. A data processing device comprising:

an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 2/5, based on a parity check matrix of an LDPC code; and

an interchanging unit that interchanges code bits of the encoded LDPC code with symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM,

wherein the encoded LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table,

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658

5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016

3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931

4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254

4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963

9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134

1652 8171 1435

3366 6543 3745

9286 8509 4645

7397 5790 8972

6597 4422 1799

9276 4041 3847

8683 7378 4946

5348 1993 9186

6724 9015 5646

4502 4439 8474

5107 7342 9442

1387 8910 2660, and

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging unit sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, and b7 with bits y7, y5 y4, y0, y3, y1, y2, and y6, respectively.

3. A data processing method comprising:

an encoding step that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 1/3, based on a parity check matrix of an LDPC code; and

an interchanging step that interchanges code bits of the encoded LDPC code with symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM,

wherein the encoded LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table,

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912

8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575

3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291

2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420

6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306

1505 5682 7778

7172 6830 6623

7281 3941 3505

10270 8669 914

3622 7563 9388

9930 5058 4554

4844 9609 2707

6883 3237 1714

4768 3878 10017

10127 3334 8267, and

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging step sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, and b7 with bits y6, y0, y3, y4, y5, y2, y1, and y7, respectively.

4. A data processing method comprising:

an encoding step that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 2/5, based on a parity check matrix of an LDPC code; and

an interchanging step that interchanges code bits of the encoded LDPC code with symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM,

wherein the encoded LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table,

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658

5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016

3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931

4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254

4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963

9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134

1652 8171 1435

3366 6543 3745

9286 8509 4645

7397 5790 8972

6597 4422 1799

9276 4041 3847

8683 7378 4946

5348 1993 9186

6724 9015 5646

4502 4439 8474

5107 7342 9442

1387 8910 2660, and

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the interchanging step sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, and b7 with bits y7, y5 y4, y0, y3, y1, y2, and y6, respectively.

5. A data processing device comprising:

a reverse interchanging unit that interchanges symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM with code bits of an LDPC code in which a code length is 16200 bits and an encoding rate is 1/3; and

a decoding unit that decodes the LDPC code interchanged by the reverse interchanging unit, based on a parity check matrix of the LDPC code,

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the reverse interchanging unit sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits y6, y0, y3, y4, y5, y2, y1, and y7 with bits b0, b1, b2, b3, b4, b5, b6, and b7, respectively,

wherein the LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table, and

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912

8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575

3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291

2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420

6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306

1505 5682 7778

7172 6830 6623

7281 3941 3505

10270 8669 914

3622 7563 9388

9930 5058 4554

4844 9609 2707

6883 3237 1714

4768 3878 10017

10127 3334 8267.

6. A data processing device comprising:

a reverse interchanging unit that interchanges symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM with code bits of an LDPC code in which a code length is 16200 bits and an encoding rate is 2/5; and

a decoding unit that decodes the LDPC code interchanged by the reverse interchanging unit, based on a parity check matrix of the LDPC code,

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the reverse interchanging unit sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits y7, y5, y4, y0, y3, y1, y2, and y6 with bits b0, b1, b2, b3, b4, b5, b6, and b7, respectively,

wherein the LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table, and

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658

5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016

3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931

4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254

4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963

9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134

1652 8171 1435

3366 6543 3745

9286 8509 4645

7397 5790 8972

6597 4422 1799

9276 4041 3847

8683 7378 4946

5348 1993 9186

6724 9015 5646

4502 4439 8474

5107 7342 9442

1387 8910 2660.

7. A data processing method comprising:

a reverse interchanging step that interchanges symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM with code bits of an LDPC code in which a code length is 16200 bits and an encoding rate is 1/3; and

a decoding step that decodes the LDPC code interchanged by the reverse interchanging step, based on a parity check matrix of the LDPC code,

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the reverse interchanging step sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits y6, y0, y3, y4, y5, y2, y1, and y7 with bits b0, b1, b2, b3, b4, b5, b6, and b7, respectively,

wherein the LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table, and

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

416 8909 4156 3216 3112 2560 2912 6405 8593 4969 6723 6912

8978 3011 4339 9312 6396 2957 7288 5485 6031 10218 2226 3575

3383 10059 1114 10008 10147 9384 4290 434 5139 3536 1965 2291

2797 3693 7615 7077 743 1941 8716 6215 3840 5140 4582 5420

6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306

1505 5682 7778

7172 6830 6623

7281 3941 3505

10270 8669 914

3622 7563 9388

9930 5058 4554

4844 9609 2707

6883 3237 1714

4768 3878 10017

10127 3334 8267.

8. A data processing method comprising:

a reverse interchanging step that interchanges symbol bits of a symbol corresponding to any one of 16 signal points determined by 16 QAM with code bits of an LDPC code in which a code length is 16200 bits and an encoding rate is 2/5; and

a decoding step that decodes the LDPC code interchanged by the reverse interchanging step, based on a parity check matrix of the LDPC code,

wherein, when code bits of 8 bits stored in eight storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit by one bit are allocated to two consecutive symbols, the reverse interchanging step sets a (#i+1)-th bit from a most significant bit of the code bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits y7, y5, y4, y0, y3, y1, y2, and y6 with bits b0, b1, b2, b3, b4, b5, b6, and b7, respectively,

wherein the LDPC code includes information bits and parity bits,

wherein the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

wherein the information matrix portion is represented by a parity check matrix initial value table, and

wherein the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows,

5650 4143 8750 583 6720 8071 635 1767 1344 6922 738 6658

5696 1685 3207 415 7019 5023 5608 2605 857 6915 1770 8016

3992 771 2190 7258 8970 7792 1802 1866 6137 8841 886 1931

4108 3781 7577 6810 9322 8226 5396 5867 4428 8827 7766 2254

4247 888 4367 8821 9660 324 5864 4774 227 7889 6405 8963

9693 500 2520 2227 1811 9330 1928 5140 4030 4824 806 3134

1652 8171 1435

3366 6543 3745

9286 8509 4645

7397 5790 8972

6597 4422 1799

9276 4041 3847

8683 7378 4946

5348 1993 9186

6724 9015 5646

4502 4439 8474

5107 7342 9442

1387 8910 2660.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2017
From: SONY CORPORATION
To: SATURN LICENSING LLC
Reel/Frame 043177/0794 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2013
From: SHINOHARA, YUJI; YAMAMOTO, MAKIKO
To: SONY CORPORATION
Reel/Frame 031395/0267 →