Linear system coefficient estimating method, integrated circuit, and electronic device
A touch panel controller ( 3 ) capable of accurately detecting a change in capacitance includes: a driving section ( 4 ) which drives capacitors (C 1 through CM) in parallel in accordance with N M-dimensional vectors; and an estimating section ( 5 ) which obtains linear sums of the capacitors (C 1 through CM) in accordance with the driving in parallel and estimates values of the capacitors (C 1 through CM) based on an inner product operation carried out with respect to (i) the linear sums of the capacitors (C 1 through CM) and (ii) the N M-dimensional vectors, the driving section ( 4 ) driving the capacitors (C 1 through CM) in parallel in a first order of the N M-dimensional vectors, the estimating section ( 5 ) estimating a first estimated value of the capacitors (C 1 through CM) in accordance with the driving in parallel in the first order, the driving section ( 4 ) driving the capacitors (C 1 through CM) in parallel in a second order of the N M-dimensional vectors, the estimating section ( 5 ) estimating a second estimated value of the capacitors (C 1 through CM) in accordance with the driving in parallel in the second order, and the touch panel controller ( 3 ) further including an averaging section ( 17 ) estimating the values of the capacitors (C 1 through CM) by averaging the first estimated value and the second estimated value.
1. A capacitance estimating method in which N linear sums of M capacitors provided at intersections of sense lines and M drive lines are obtained by driving the M capacitors in parallel in accordance with voltages which constitute N M-dimensional vectors and values of the M capacitors are estimated based on an inner product operation carried out with respect to (i) the N linear sums of the M capacitors and (ii) M N-dimensional vectors,
the M N-dimensional vectors being vectors which make it possible to obtain, as a result of an inner product operation carried out with respect to the M N-dimensional vectors and the N M-dimensional vectors, a matrix which is a square matrix with M rows and M columns and in which an absolute value of a diagonal element is relatively larger than an absolute value of a non-diagonal element,
said capacitance estimating method comprising:
a first estimating step of estimating a first estimated value of the M capacitors by driving the M capacitors in parallel in accordance with a first matrix in which the N M-dimensional vectors are arranged in a first order;
a second estimating step of estimating a second estimated value of the M capacitors by driving the M capacitors in parallel in accordance with a second matrix in which the N M-dimensional vectors are arranged in a second order that is different from the first order; and
an averaging step of estimating the values of the M capacitors by averaging the first estimated value and the second estimated value.
2. The capacitance method as set forth in claim 1 , wherein the second order is an order in which the N M-dimensional vectors arranged in the first order are reversely rearranged.
3. The capacitance estimating method as set forth in claim 1 , wherein the second order is an order in which the N M-dimensional vectors arranged in the first order are randomly rearranged.
4. A capacitance estimating method in which N linear sums of M capacitors provided at intersections of sense lines and M drive lines are obtained by driving the M capacitors in parallel in accordance with voltages which constitute N M-dimensional vectors and values of the M capacitors are estimated based on an inner product operation carried out with respect to (i) the N linear sums of the M capacitors and (ii) the M N-dimensional vectors,
the M N-dimensional vectors being vectors which make it possible to obtain, as a result of an inner product operation carried out with respect to the M N-dimensional vectors and the N M-dimensional vectors, a matrix which is a square matrix with M rows and M columns and in which an absolute value of a diagonal element is relatively larger than an absolute value of a non-diagonal element,
the N M-dimensional vectors each containing M elements which are arranged in a transverse direction,
the N M-dimensional vectors being arranged in a longitudinal direction,
the N M-dimensional vectors being arranged so that a value obtained by adding (a) the number of times of a change in the M elements of each of the N M-dimensional vectors from an increase to a decrease in value in the transverse direction and (b) the number of times of a change in the M elements of each of the N M-dimensional vectors from the decrease to the increase in value in the transverse direction monotonously changes in the longitudinal direction,
said capacitance estimating method comprising a monotonous change estimating step of estimating the values of the M capacitors by driving the M capacitors in parallel in an order of the N M-dimensional vectors arranged in the longitudinal direction.
5. The capacitance estimating method as set forth in claim 4 , wherein the N M-dimensional vectors constitute an Hadamard-Walsh transform matrix.
6. The capacitance estimating method as set forth in claim 4 , wherein the N M-dimensional vectors constitute Discrete Cosine Transform (DCT).
7. The capacitance estimating method as set forth in claim 4 , wherein the N M-dimensional vectors constitute a submatrix of the Hadamard-Walsh transform matrix.
8. The capacitance estimating method as set forth in claim 4 , wherein the N M-dimensional vectors constitute a submatrix of the Discrete Cosine Transform.
9. The capacitance estimating method as set forth in claim 4 , wherein:
the monotonous change estimating step includes:
a first estimating step of estimating a first estimated value of the M capacitors by driving the M capacitors in parallel in a first order of the N M-dimensional vectors;
a second estimating step of estimating a second estimated value of the M capacitors by driving the M capacitors in parallel in a second order of the N M-dimensional vectors in which second order the N M-dimensional vectors arranged in the first order are reversely rearranged; and
an averaging step of estimating the values of the M capacitors by averaging the first estimated value and the second estimated value.
10. An intergrated circuit comprising:
a driving section which drives, in parallel in accordance with voltages which constitute N M-dimensional vectors, M capacitors provided at intersections of sense lines and M drive lines; and
estimating section which obtains N linear sums of the M capacitors in accordance with the driving in parallel by the driving section and estimates values of the M capacitors based on an inner product operation carried out with respect to (i) the N linear sums of the M capacitors and (ii) the M N-dimensional vectors,
the M N-dimensional vectors being vectors which make it possible to obtain, as a result of an inner product operation carried out with respect to the M N-dimensional vectors and the N M-dimensional vectors, a matrix which is a square matrix with M rows and M columns and in which an absolute value of a diagonal element is relatively larger than an absolute value of a non-diagonal element,
the N M-dimensional vectors each containing M elements which are arranged in a transverse direction,
the N M-dimensional vectors being arranged in a longitudinal direction,
the N M-dimensional vectors being arranged so that (a) the number of times of a change in the M elements of each of the N M-dimensional vectors from an increase to a decrease in value in the transverse direction and (b) the number of times of a change in the M elements of each of the N M-dimensional vectors from the decrease to the increase in value in the transverse direction monotonously changes in the longitudinal direction, and
the estimating section estimating the values of the M capacitors by driving the M capacitors in parallel in an order of the N M-dimensional vectors arranged in the longitudinal direction.
11. An electronic device comprising:
an integrated circuit recited in claim 10 ;
touch panel which is controlled by the integrated circuit; and
a display panel which is placed on the touch panel or contains the touch panel.