IP Library › Granted Patent US 9,026,884

Granted Patent B2

US 9,026,884 · App. 14/112,972 · Granted May 5, 2015

Data processing device and data processing method

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Quick Facts

Patent No.: US 9,026,884
App. No.: 14/112,972
Granted: May 5, 2015
Kind: B2

External Links

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Abstract

The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. In a case where a predetermined LDPC code having a code length of 16200 bits and a code rate of 8/15 is mapped on 256 signal points, and the (#i+1)th bit counted from the uppermost bit among 8×1 sign bits and the (#i+1)th bit counted from the uppermost bit among 8×1 symbol bits of one symbol are expressed as a bit b#i and a bit y#i, respectively, a demultiplexer performs shuffling to assign a bit b0 to a bit y2, a bit b1 to a bit y6, a bit b2 to a bit y1, a bit b3 to a bit y0, a bit y4 to a bit y7, a bit b5 to a bit y5, a bit b6 to a bit y3, and a bit b7 to a bit y4. The present technique can be applied to transmission systems that transmit LDPC codes, for example.

Claims (164)

1. A data processing device comprising:

an encoding unit configured to perform LDPC encoding to generate an LDPC code having a code length of 16200 bits and a code rate of 8/15 based on a parity check matrix for LDPC codes; and

a shuffling unit configured to replace sign bits of the LDPC code encoded by the encoding unit with symbol bits of a symbol corresponding to one of 256 signal points defined by 256QAM,

the LDPC code encoded by the encoding unit including information bits and parity bits,

the parity check matrix including an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion being represented by a check matrix initial value table,

the check matrix initial value table being a table that shows positions of elements “1” of the information matrix portion at intervals of 360 columns, and contains

32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189

1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537

2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534

574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554

14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462

4075 4188 7313 7553

5145 6018 7148 7507

3198 4858 6983 7033

3170 5126 5625 6901

2839 6093 7071 7450

11 3735 5413

2497 5400 7238

2067 5172 5714

1889 7173 7329

1795 2773 3499

2695 2944 6735

3221 4625 5897

1690 6122 6816

5013 6839 7358

1601 6849 7415

2180 7389 7543

2121 6838 7054

1948 3109 5046

272 1015 7464

the shuffling unit replacing

a bit b0 with a bit y2,

a bit b1 with a bit y6,

a bit b2 with a bit y1,

a bit b3 with a bit y0,

a bit b4 with a bit y7,

a bit b5 with a bit y5,

a bit b6 with a bit y3, and

a bit b7 with a bit y4,

where eight sign bits that are stored in eight storage units each having a storage capacity of 16200/8 bits and are read from the respective storage units by one bit each are assigned to one symbol, the (#1+1)th bit counted from the uppermost bit among the eight sign bits is expressed as a bit b#i, and the (#i+1)th bit counted from the uppermost bit among eight symbol bits of the one symbol is expressed as a bit y#i.

2. A data processing method comprising:

an encoding step of performing LDPC encoding to generate an LDPC code having a code length of 16200 bits and a code rate of 8/15 based on a parity check matrix for LDPC codes; and

a shuffling step of replacing sign bits of the LDPC code encoded in the encoding step with symbol bits of a symbol corresponding to one of 256 signal points defined by 256QAM,

the LDPC code encoded in the encoding step including information bits and parity bits,