IP Library Granted Patent US 9,100,049
Granted Patent B2
US 9,100,049 · App. 14/115,760 · Granted Aug 4, 2015

Parallel bit interleaver

Inventor: Mihail Petrov (Langen, DE)
Assignee: PANASONIC CORPORATION
H03M13/116H03M13/1165H03M13/255H03M13/27H03M13/2957H03M13/356H03M13/6325H03M13/6552H03M13/6555H03M13/1168H04L1/0058H04L1/0606H04L1/0618
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Quick Facts
Patent No.
US 9,100,049
App. No.
14/115,760
Granted
Aug 4, 2015
Kind
B2
Abstract

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Claims (26)

1. A bit interleaving method interleaving a codeword of quasi-cyclic low-density parity check codes, including repeat-accumulate quasi-cyclic low-density parity check codes, the bit interleaving method comprising:

a permutation step of applying a permutation process to the codeword made up of N cyclic blocks each including Q cyclic block bits in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; and

an allocation step of allocating codeword bits of the codeword, after the-permutation process, to Q×N/M constellation words, each of the constellation words being made up of M constellation word bits, wherein

F is a divisor of M and Q,

N is not a multiple of M/F,

N′ is equal to (M/F)×floor(N/(M/F)),

each of N′ cyclic blocks among the N cyclic blocks is allocated to one among F×N′/M folding sections according to the cyclic block permutation rule, each of the folding sections including M/F of the cyclic blocks,

(N−N′) of the cyclic blocks are excluded from the N′ cyclic blocks and include a parity section of the codeword,

the cyclic block permutation rule defines allocation of the N′ cyclic blocks to the folding sections, and

in the allocation step, the allocation process is applied such that the M bits include F cyclic block bits from each of M/F of the cyclic blocks in each of the folding sections, and such that the M bits are allocated to each of Q/F of the constellation words.

2. A decoding method, comprising:

a demodulation step of generating a demodulated signal by demodulating a signal transmitted by modulating a plurality of bits allocated to each of a plurality of constellation words using the bit interleaving method of claim 1 ; and

a decoding step of decoding the demodulated signal according to the cyclic block permutation rule and generating original data according to quasi-cyclic low-density parity check codes.

3. A bit interleaver interleaving a codeword of quasi-cyclic low-density parity check codes, including repeat-accumulate quasi-cyclic low-density parity check codes, the bit interleaver comprising:

a permutation unit applying a permutation process to the codeword made up of N cyclic blocks each including Q cyclic block bits in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; and

an allocation unit allocating codeword bits of the codeword, after the permutation process, to Q×N/M constellation words, each of the constellation words being made up of M constellation word bits, wherein

F is a divisor of M and Q,

N is not a multiple of M/F,

N′ is equal to (M/F)×floor(N/(M/F)),

each of N′ cyclic blocks among the N cyclic blocks is allocated to one among F×N′/M folding sections according to the cyclic block permutation rule, each of the folding sections including M/F of the cyclic blocks,

(N−N′) of the cyclic blocks are excluded from the N′ cyclic blocks and include a parity section of the codeword,

the cyclic block permutation rule defines allocation of the N′ cyclic blocks to the folding sections, and

the allocation unit applies the allocation process such that the M bits include F cyclic block bits from each of M/F of the cyclic blocks in each of the folding sections, and such that the M bits are allocated to each of Q/F of the constellation words.

4. A decoder, comprising:

a demodulating unit generating a demodulated signal by demodulating a signal transmitted by modulating a plurality of bits allocated to each of a plurality of constellation words using the bit interleaver of claim 3 ; and

a decoding unit decoding the demodulated signal according to the cyclic block permutation rule and generating original data according to quasi-cyclic low-density parity check codes.

Assignments (2)
CHANGE OF NAME Recorded May 9, 2022
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 059911/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2014
From: PETROV, MIHAIL
To: PANASONIC CORPORATION
Reel/Frame 032512/0957 →
Priority Claims (1)
EP 11004127 · May 18, 2011 · regional
Continuity (1)
Related Publication 20140075271A1 · Mar 13, 2014