IP Library › Granted Patent US 9,135,108

Granted Patent B2

US 9,135,108 · App. 14/116,231 · Granted Sep 15, 2015

Data processing device and data processing method

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Quick Facts

Patent No.: US 9,135,108
App. No.: 14/116,231
Granted: Sep 15, 2015
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved. In the case in which an LDPC code having a code length of 16200 bits and an encoding rate of 8/15 is mapped to 16 signal points, if (#i+1)-th bits from most significant bits of sign bits of 4×2 bits and symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, respectively, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y0, y4, y3, y1, y2, y5, y6, and y7, respectively. The present technique can be applied to a transmission system or the like transmitting an LDPC code.

Claims (372)

1. A data processing device comprising:

an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 8/15, on the basis of a parity check matrix of an LDPC code; and

an interchanging unit that interchanges sign bits of the LDPC code encoded by the encoding unit with symbol bits of a symbol corresponding to any one of 16 signal points determined by 16QAM,

wherein the LDPC code encoded by the encoding unit includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table,

the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows:

32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189

1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537

2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534

574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554

14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462

4075 4188 7313 7553

5145 6018 7148 7507

3198 4858 6983 7033

3170 5126 5625 6901

2839 6093 7071 7450

11 3735 5413

2497 5400 7238

2067 5172 5714

1889 7173 7329

1795 2773 3499

2695 2944 6735

3221 4625 5897

1690 6122 6816

5013 6839 7358

1601 6849 7415

2180 7389 7543

2121 6838 7054

1948 3109 5046

272 1015 7464, and

when sign bits of 8 bits stored in 8 storage units having storage capacities of 16200/8 bits and read from the respective storage units one bit at a time are allocated to two consecutive symbols, the interchanging unit sets a (#i+1)-th bit from a most significant bit of the sign bits of the 8 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 8 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, and b7 with bits y0, y4, y3, y1, y2, y5, y6, and y7, respectively.

2. A data processing device comprising:

an encoding unit that performs LDPC encoding in which a code length is 16200 bits and an encoding rate is 7/15, on the basis of a parity check matrix of an LDPC code; and

an interchanging unit that interchanges sign bits of the LDPC code encoded by the encoding unit with symbol bits of a symbol corresponding to any one of 64 signal points determined by 64QAM,

wherein the LDPC code encoded by the encoding unit includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table,

the parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix portion for every 360 columns and is configured as follows:

3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638

356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602

18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582

714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559

3452 7935 8092 8623

56 1955 3000 8242

1809 4094 7991 8489

2220 6455 7849 8548

1006 2576 3247 6976

2177 6048 7795 8295

1413 2595 7446 8594

2101 3714 7541 8531

10 5961 7484

3144 4636 5282

5708 5875 8390

3322 5223 7975

197 4653 8283

598 5393 8624

906 7249 7542

1223 2148 8195

976 2001 5005, and

when sign bits of 12 bits stored in 12 storage units having storage capacities of 16200/12 bits and read from the respective storage units one bit at a time are allocated to two consecutive symbols, the interchanging unit sets a (#i+1)-th bit from a most significant bit of the sign bits of the 12 bits as a bit b#i and a (#i+1)-th bit from a most significant bit of symbol bits of 12 bits of the two symbols as a bit y#i and interchanges bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, and b11 with bits y2, y0, y8, y7, y1, y6, y4, y3, y10, y9, y5, and y11, respectively.

3. A data processing device comprising: