IP Library Patent Application 14116632
Patent Application
App. No. 14/116,632

PARALLEL BIT INTERLEAVER

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Quick Facts
Patent No.
US None
App. No.
14/116,632
Abstract

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Claims (19)

1 - 14 . (canceled)

15 . A bit interleaving method interleaving a codeword of quasi-cyclic low-density parity check codes, including repeat-accumulate quasi-cyclic low-density parity check codes, the bit interleaving method comprising:

an allocation step of allocating codeword bits of the codeword made up of N cyclic blocks each including Q cyclic block bits to Q×N/M constellation words, each of the constellation words being made up of M bits, wherein

F is an integer greater than 1, and is a divisor of M and Q,

N is not a multiple of M/F,

N′ is equal to (M/F)×floor(N/(M/F)),

in the allocation step, allocation process is applied such that the M bits-include F cyclic block bits from each of M/F different cyclic blocks in each of F×N′/M folding sections, each of the folding sections being made up of M/F of the cyclic blocks, and such that the M bits are allocated to each of Q/F of the constellation words.

16 . A bit interleaver interleaving a codeword of quasi-cyclic low-density parity check codes, including repeat-accumulate quasi-cyclic low-density parity check codes, the bit interleaver comprising:

an allocation unit allocating codeword bits of the codeword made up of N cyclic blocks each including Q cyclic block bits to Q×N/M constellation words, each of the constellation words being made up of M bits, wherein

F is an integer greater than 1, and is a divisor of M and Q,

N is not a multiple of M/F,

N′ is equal to (M/F)×floor(N/(M/F)),

the allocation process is applied such that the M bits include F cyclic block bits from each of M/F different cyclic blocks in each of F×N′/M folding sections, each of the folding sections being made up of M/F of the cyclic blocks, and such that the M bits are allocated to each of Q/F of the constellation words.

17 . A decoding method, comprising:

a demodulation step of generating a demodulated signal by demodulating a signal transmitted by modulating M bits allocated to each of a plurality of constellation words using the bit interleaving method of claim 15 ; and

a decoding step of decoding the demodulated signal and generating original data according to quasi-cyclic low-density parity check codes.

18 . A decoder, comprising:

a demodulating unit generating a demodulated signal by demodulating a signal transmitted by modulating M bits allocated to each of a plurality of constellation words using the bit interleaver of claim 16 ; and

a decoding unit decoding the demodulated signal and generating original data according to quasi-cyclic low-density parity check codes.

Assignments (2)
CHANGE OF NAME Recorded May 9, 2022
From: PANASONIC CORPORATION
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 059911/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2014
From: PETROV, MIHAIL
To: PANASONIC CORPORATION
Reel/Frame 032512/0959 →