ADC calibration
A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight w i is less than the sum of the bit weights W j , j=0, 1, . . . , i−1 corresponding to the bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight w i ; performing a first analog-to-digital, A/D, conversion using the bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i to obtain a first digital word of said bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i representing said first electrical value; and estimating the value of the bit weight W i expressed in terms of the bit weights Wj. j=0, 1, . . . , i−1 corresponding to the bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i based at least on said first digital word, wherein the resulting estimated value of the bit weight w i is one of the at least one calibration value. A control unit, a redundant ADC and a computer program are also disclosed.
1. A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, comprising taps of a capacitive network wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i , comprising:
for taps corresponding to bits with higher significance than the bit b i :
connecting each tap to a different floating node; or
connecting all taps to the same floating node;
sampling a first electrical value representative of the bit weight w i ; and
performing a first analog-to-digital, A/D, conversion using the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i to obtain a first digital word of said bits b j , j=0, 1, . . . , i−1 with lesser significance than the bit b i representing said first electrical value;
estimating the value of the bit weight w i expressed in terms of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i based at least on said first digital word, wherein the resulting estimated value of the bit weight w i is one of the at least one calibration value.
2. The method according to claim 1 , further comprising
sampling a second electrical value representative of the sum of one or more bit weights w k corresponding to one or more bits b k with lesser significance than the bit b i ; and
performing a second A/D conversion using the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i to obtain a second digital word of said bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i representing said second electrical value; wherein
estimating the value of the bit weight w i expressed in terms of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i comprises estimating said value of the bit weight w i based on the first and the second digital word.
3. The method according to claim 2 , wherein performing the first and the second A/D conversion comprises performing a first level shift with a first amount and a second level shift with a second amount, respectively, for ensuring that the electrical value to be converted is in a conversion range corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i even in the presence of an offset.
4. The method according to claim 3 , wherein the first amount is equal, or substantially equal, to the second amount.
5. The method according to claim 4 , wherein the first and second amount correspond to approximately half the bit weight w i .
6. The method according to claim 3 , further comprising estimating a value of an offset of the ADC based on the first and the second digital word.
7. The method according to claim 6 , wherein the estimated value of the offset is one of said at least one calibration value.
8. A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, comprising N taps of a capacitive network wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i , and wherein a relation r k , k=1, . . . , N−1, between the bit weights w k , k=0,1, . . . , N−1, is expressed by w k =w k−1 r k , the method comprising:
performing the method according to claim 1 for i=L−1 wherein estimating the value of the bit weight w L−1 expressed in terms of the bit weights w j , j=0,1, . . . , L−2 produces a L−1,j that fulfill
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numerically solving
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using successive approximation; and
using an assumption that r k =r, k=1, . . . , L−1 for remaining bits b i , i>L−1.
9. A method of calibrating a redundant ADC, wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i , comprising
for each of one or more such bits b i :
a) performing the method according to claim 1 for estimating the value of the bit weight w i expressed in terms of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i ; and
b) storing said at least one or more calibration values, resulting from step a) in a memory.
10. A method of error correction in a redundant ADC, wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i comprising
calibrating the ADC using the method according to claim 9 ; and
during operation of the ADC for A/D conversion of an analog input signal of the ADC, utilizing the stored one or more calibration values for determining an error-corrected output signal of the ADC.
11. The method according to claim 1 , wherein the ADC is a successive approximation, SA, ADC.
12. The method according to claim 1 , wherein the ADC is a pipeline ADC.
13. A control unit for a redundant ADC, wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i , wherein the control unit is configured to control the execution of the method according to claim 1 .
14. The control unit according to claim 13 , wherein the ADC is an SA ADC.
15. The control unit according to claim 13 , wherein the ADC is a pipeline ADC.
16. A redundant ADC, wherein, for at least an i:th bit b i , the corresponding bit weight w i is less than the sum of the bit weights w j , j=0,1, . . . , i−1 corresponding to the bits b j , j=0,1, . . . , i−1 with lesser significance than the bit b i , comprising
a control unit according to claim 13 .
17. The redundant ADC according to claim 16 , wherein the ADC is an SA ADC.
18. The redundant ADC according to claim 16 , wherein the ADC is a pipeline ADC.
19. A computer program product comprising computer program code means for executing the method according to claim 1 in the redundant ADC when said computer program code means are run by a programmable control unit of the redundant ADC.
20. A computer readable medium having stored thereon a computer program product according to claim 19 .