Inverter drive device
View Patent ↗An inverter drive device includes a drive circuit that outputs a gate voltage signal of a power semiconductor element; and a Zener clamping protection circuit that acquires an emitter electrode side voltage of the power semiconductor element, and, if that voltage is greater than a predetermined voltage value, performs clamping of the gate voltage of the drive circuit after a predetermined time interval has elapsed from the acquisition of the emitter electrode side voltage. The Zener clamping protection circuit includes a latch circuit that, after the emitter electrode side voltage has been acquired, continues the clamping of the gate voltage by the Zener clamping protection circuit during an interval.
1. An inverter drive device that drives an inverter circuit including a power semiconductor element, comprising:
a drive circuit that outputs a gate voltage of the power semiconductor element on the basis of a PWM signal;
an over-current protection circuit that acquires an emitter electrode side voltage of the power semiconductor element, and, if that voltage is greater than a first predetermined voltage value that is determined in advance, outputs a fault signal to the drive circuit for stopping the output of the gate voltage after a first predetermined time interval has elapsed from the acquisition of the emitter electrode side voltage; and
a Zener clamping protection circuit that acquires the emitter electrode side voltage of the power semiconductor element, and, if that voltage is greater than a second predetermined voltage value that is determined in advance, performs clamping of the gate voltage of the drive circuit after a second predetermined time interval has elapsed from the acquisition of the emitter electrode side voltage; wherein
the Zener clamping protection circuit comprises a latch circuit that, after the emitter electrode side voltage has been acquired, continues the clamping of the gate voltage by the Zener clamping protection circuit during an interval that is greater than the first predetermined time interval.
2. An inverter drive device according to claim 1 , wherein the second predetermined voltage value is set to be greater than the first predetermined voltage value.
3. An inverter drive device according to claim 1 , wherein the second predetermined time interval is set to be smaller than the first predetermined time interval.
4. An inverter drive device according to claim 1 , wherein the latch circuit sets the clamp continuation time interval to be longer than a short circuit toleration time interval of the power semiconductor element.
5. An inverter drive device according to claim 1 , wherein the latch circuit performs cancellation of clamping of the gate voltage by the Zener clamping protection circuit in synchronism with the OFF signal of the PWM signal that is inputted to the drive circuit.
6. An inverter drive device according to claim 1 , wherein the latch circuit performs cancellation of clamping of the gate voltage by the Zener clamping protection circuit in synchronism with the fault signal that is inputted to the drive circuit.