Driver integrated circuit
Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2 ).
1. A charged particle beam apparatus for measuring a wafer based on secondary electrons generated by irradiating an electron beam to the wafer, the charged particle beam apparatus comprising:
a differential input circuit that amplifies a differential input signal;
a level shift circuit that shifts the voltage of the signal amplified by the differential input circuit; and
an output circuit that amplifies and outputs the signal whose voltage is shifted by the level shift circuit,
wherein:
the level shift circuit and the output circuit are divided by using three or more chips;
different voltages are applied to substrates of the three or more chips;
a deviation control of the electron beam is performed with the signal amplified by the output circuit;
the three or more chips include a first chip as a high voltage-applied chip, a second chip as an intermediate voltage-applied chip, and a third chip as a low voltage-applied chip;
an applied voltage to the first chip is set at V 1 ±δ(V 1 is substantially equal to V 2 ; δ is a variation factor), an applied voltage to the second chip is set at 0 ±δ, and an applied voltage to the third chip is set at −V 1 ±δ, where V 2 is the process withstand voltage; and
the output voltage from the output circuit has a maximum value of ±2V 1 .
2. The charged particle beam apparatus according to claim 1 , wherein:
the differential input circuit is disposed on the second chip;
the level shift circuit is divided into portions disposed on the first to the third chips;
a level shift circuit portion of the first chip retains a H-level side signal generated by a level shift circuit portion of the second chip by shifting the voltage of the amplified signal;
a level shift circuit portion of the third chip retains a L-level side signal generated by the level shift circuit portion of the second chip by shifting the voltage of the amplified signal;
the output circuit is divided into portions disposed on the first to the third chips;
the H-level side signal is amplified by an output circuit portion of the first chip and an output circuit portion of the second chip;
the L-level side signal is amplified by the output portion of the second chip and an output circuit portion of the third chip; and
the output voltage is generated from the amplified signals.
3. The charged particle beam apparatus according to claim 2 , wherein:
an applied voltage to the level shift circuit portion of the first chip is set to be greater than V 1 and smaller than 2V 1 ;
an applied voltage to the level shift circuit portion of the second chip is set to be greater than −V 1 and smaller than V 1 ;
an applied voltage to the level shift circuit portion of the third chip is set to be greater than −2V 1 and smaller than −V 1 ;
an applied voltage to the output circuit portion of the first chip is set to be greater than V 1 and smaller than 2V 1 ;
an applied voltage to the level shift circuit portion of the second chip is set to be greater than −V 1 and smaller than V 1 ; and
an applied voltage to the level shift circuit portion of the third chip is set to be greater than −2V 1 and smaller than −V 1 .
4. The charged particle beam apparatus according to claim 1 , comprising:
a driver integrated circuit that includes the differential input circuit, the level shift circuit, and the output circuit,
wherein:
the driver integrated circuit has a multilayer substrate including a plurality of solid layers; and
a heat dissipator attached to a rear surface of the multilayer substrate on a side opposite to a chip mounting surface,
wherein:
the three or more chips are separately disposed on the chip mounting surface of the multilayer substrate;
a substrate potential is applied to the substrate of each of the three or more chips from a number of the plurality of the solid layers corresponding to the number of the chips;
a plurality of chip potential patterns corresponding to the number of the chips is formed on the rear surface of the multilayer substrate, the chip potential patterns enabling electrical conduction from the solid layers for applying the substrate voltage to each of the three or more chips;
each of the number of solid layers corresponding to the number of the chips to which the substrate voltage is applied, each of the plurality of chip potential patterns, and each of the three or more chips are connected by a plurality of connecting vias such that the chips are electrically isolated from each other; and
heat generated from the three or more chips is dissipated outside the driver integrated circuit from the heat dissipator via the plurality of chip potential patterns.
5. The charged particle beam apparatus according to claim 4 , comprising an insulating layer of an insulating material disposed between the heat dissipator and the chip potential pattern or the rear surface of the multilayer substrate.
6. A charged particle beam apparatus for measuring a wafer based on secondary electrons generated by irradiating an electron beam to the wafer, the charged particle beam apparatus comprising:
a differential input circuit that amplifies a differential input signal;
a level shift circuit that shifts the voltage of the signal amplified by the differential input circuit; and
an output circuit that amplifies and outputs the signal whose voltage is shifted by the level shift circuit;
wherein:
the level shift circuit and the output circuit are divided by using three or more chips;
different voltages are applied to substrates of the three or more chips;
a deviation control of the electron beam is performed with the signal amplified by the output circuit;
the three or more chips include a first chip as a high voltage-applied chip, a second chip as an intermediate voltage-applied chip, and a third chip as a low voltage-applied chip;
an applied voltage to the first chip is set at V 1 ±δ(V 1 is substantially equal to V 2 ; δ is a variation factor), an applied voltage to the second chip is set at a potential determined by resistive division of the output voltage, and an applied voltage to the third chip is set at −V 1 ±δ, where V 2 is the process withstand voltage; and
the output voltage has a maximum value of ±2V 1 .
7. A charged particle beam apparatus for measuring a wafer based on secondary electrons generated by irradiating an electron beam to the wafer comprising:
a differential input circuit that amplifies a differential input signal;
a level shift circuit that shifts the voltage of the signal amplified by the differential input circuit;
an output circuit that amplifies and outputs the signal whose voltage is shifted by the level shift circuit; and
a substrate potential control unit,
wherein:
the level shift circuit and the output circuit are divided by using M chips, including a first chip, a second chip, a third chip, a fourth chip, through an M-th chip, wherein M=2N− 1 and N is an integer of at least 3;
an output voltage from the output circuit in the N-th chip has a maximum value of ±NV 1 ;
the substrate potential control unit is configured to set a different applied voltage to each of the M chips, the applied voltage varying in accordance with a value of the output voltage generated by the output circuit from the first chip until the N-th chip,
when the output voltage from the output circuit is −NV 1 , an applied voltage to the i-th chip is set at (N−(2*i− 1 ))V 1 ±δ until i equals N, wherein i is a positive integer;
when the output voltage from the output circuit is NV 1 , an applied voltage to the (N+j)-th chip is set at (N−(2*j+ 1 ))V 1 ±δ until j equals (N− 1 ), wherein j is a positive integer; and
a deviation control of the electron beam is performed with the signal amplified by the output circuit; wherein
N is three;
the M chips include the first chip, the second chip, the third chip, the fourth chip and a fifth chip;
the output voltage from the output circuit has a maximum value of ±3V 1 ;
when the output voltage from the output circuit is −3V 1 , an applied voltage to the first chip is set at 2V 1 ±δ, an applied voltage to the second chip is set at 0±δ, and an applied voltage to the third chip is set at −2V 1 ±δ; and
when the output voltage from the output circuit is 3V 1 , an applied voltage to the third chip is set at 2V 1 ±δ, an applied voltage to the fourth chip is set at 0±δ, and an applied voltage to the fifth chip is set at −2V 1 ±δ.