Transmission processing method, transmitter, reception processing method, and receiver
Information bits are encoded according to a low density parity check code with code rate 7/15 and a codeword length of 16200. The resulting codeword bits are bit-interleaved and the interleaved bits are demultiplexed into 8 sequences of bits. The 8 sequences of bits are permuted according to a predetermined permutation rule: v 0 =b 2 , v 1 =b 6 , v 2 =b 0 , v 3 =b 1 , v 4 =b 4 , v 5 =b 5 , v 6 =b 3 , v 7 =b 7 .
1. A transmission processing method comprising:
an encoding step of encoding information bits into a codeword according to a low density parity check code with code rate 7/15 and a codeword length of 16200, the low density parity check code shown in Table 1:
TABLE 1
Addresses of parity bit accumulators for the LDPC code with the code rate 7/15 and the codeword length of 16200
3
137
314
327
983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638
356
1197
1208
1839
1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602
18
187
1115
1417
1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582
714
2713
2726
2964
3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559
3452
7935
8092
8623
56
1955
3000
8242
1809
4094
7991
8489
2220
6455
7849
8548
1006
2576
3247
6976
2177
6048
7795
8295
1413
2595
7446
8594
2101
3714
7541
8531
10
5961
7484
3144
4636
5282
5708
5875
8390
3322
5223
7975
197
4653
8283
598
5393
8624
906
7249
7542
1223
2148
8195
976
2001
5005
a bit-interleaving step of conducting parity interleaving and column-row interleaving on bits of the codeword obtained in the encoding step, the column-row interleaving being conducted with or without twist;
a bit-to-cell demultiplexing step of demultiplexing a sequence of bits interleaved in the bit-interleaving step into 8 sequences of bits and permuting the 8 sequences of bits according to a predetermined permutation rule;
a mapping step of mapping each of 8-bit cell words obtained in the bit-to-cell demultiplexing step, according to a 256QAM (Quadrature Amplitude Modulation) constellation,
wherein
letting v i denote a bit in the i th sequence of bits before the permutation (for i=0, 1, . . . 7), and
letting b i denote a bit in the i th sequence of bits after the permutation (for i=0, 1, . . . 7),
the predetermined permutation rule is:
v 0 =b 2 , v 1 =b 6 , v 2 =b 0 , v 3 =b 1 , v 4 =b 4 , v 5 =b 5 , v 6 =b 3 , v 7 =b 7 .
2. A transmitter comprising:
an encoder adapted to encode information bits into a codeword according to a low density parity check code with code rate 7/15 and a codeword length of 16200, the low density parity check code shown in Table 2:
TABLE 2
Addresses of parity bit accumulators for the LDPC code with the code rate 7/15 and the codeword length of 16200
3
137
314
327
983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638
356
1197
1208
1839
1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602
18
187
1115
1417
1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582
714
2713
2726
2964
3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559
3452
7935
8092
8623
56
1955
3000
8242
1809
4094
7991
8489
2220
6455
7849
8548
1006
2576
3247
6976
2177
6048
7795
8295
1413
2595
7446
8594
2101
3714
7541
8531
10
5961
7484
3144
4636
5282
5708
5875
8390
3322
5223
7975
197
4653
8283
598
5393
8624
906
7249
7542
1223
2148
8195
976
2001
5005
a bit-interleaver adapted to conduct parity interleaving and column-row interleaving on bits of the codeword obtained by the encoder, the column-row interleaving being conducted with or without twist;
a bit-to-cell demultiplexer adapted to demultiplex a sequence of bits interleaved by the bit-interleaver into 8 sequences of bits and permute the 8 sequences of bits according to a predetermined permutation rule;
a mapper adapted to map each of 8-bit cell words obtained by the bit-to-cell demultiplexer, according to a 256QAM (Quadrature Amplitude Modulation) constellation,
wherein
letting v i denote a bit in the i th sequence of bits before the permutation (for i=0, 1, . . . 7), and
letting b i denote a bit in the i th sequence of bits after the permutation (for i=0, 1, . . . 7),
the predetermined permutation rule is:
v 0 =b 2 , v 1 =b 6 , v 2 =b 0 , v 3 =b 1 , v 4 =b 4 , v 5 =b 5 , v 6 =b 3 , v 7 =b 7 .
3. A reception processing method comprising:
a demapping step of demapping complex cells according to a 256QAM (Quadrature Amplitude Modulation) constellation;
a cell-to-bit multiplexing step of permuting 8 sequences of bits obtained in the demapping step, according to a predetermined permutation rule and multiplexing 8 sequences of bits obtained as a result of the permutation into one sequence of bits;
a bit-deinterleaving step of conducting column-row deinterleaving and parity deinterleaving on the one sequence of bits obtained as a result of the multiplexing, the column-row deinterleaving being conducted with or without twist;
a decoding step of decoding bits deinterleaved in the bit-deinterleaving step, according to a low density parity check code with code rate 7/15 and a codeword length of 16200, the low density parity check code shown in Table 3:
TABLE 3
Addresses of parity bit accumulators for the LDPC code with the code rate 7/15 and the codeword length of 16200
3
137
314
327
983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638
356
1197
1208
1839
1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602
18
187
1115
1417
1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582
714
2713
2726
2964
3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559
3452
7935
8092
8623
56
1955
3000
8242
1809
4094
7991
8489
2220
6455
7849
8548
1006
2576
3247
6976
2177
6048
7795
8295
1413
2595
7446
8594
2101
3714
7541
8531
10
5961
7484
3144
4636
5282
5708
5875
8390
3322
5223
7975
197
4653
8283
598
5393
8624
906
7249
7542
1223
2148
8195
976
2001
5005
wherein
letting b i denote a bit in the i th sequence of bits before the permutation (for i=0, 1, . . . 7), and
letting v i denote a bit in the i th sequence of bits after the permutation (for i=0, 1, . . . 7),
the predetermined permutation rule is:
v 0 =b 2 , v 1 =b 6 , v 2 =b 0 , v 3 =b 1 , v 4 =b 4 , v 5 =b 5 , v 6 =b 3 , v 7 =b 7 .
4. A receiver comprising:
a demapper adapted to demap complex cells according to a 256QAM (Quadrature Amplitude Modulation) constellation;
a cell-to-bit multiplexer adapted to permute 8 sequences of bits obtained by the demapper, according to a predetermined permutation rule and multiplex 8 sequences of bits obtained as a result of the permutation into one sequence of bits;
a bit deinterleaver adapted to conduct column-row deinterleaving and parity deinterleaving on the one sequence of bits obtained as a result of the multiplexing, the column-row deinterleaving being conducted with or without twist;
a decoder adapted to decode bits deinterleaved by the bit deinterleaver, according to a low density parity check code with code rate 7/15 and a codeword length of 16200, the low density parity check code shown in Table 4;
TABLE 4
Addresses of parity bit accumulators for the LDPC code with the code rate 7/15 and the codeword length of 16200
3
137
314
327
983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638
356
1197
1208
1839
1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602
18
187
1115
1417
1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582
714
2713
2726
2964
3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559
3452
7935
8092
8623
56
1955
3000
8242
1809
4094
7991
8489
2220
6455
7849
8548
1006
2576
3247
6976
2177
6048
7795
8295
1413
2595
7446
8594
2101
3714
7541
8531
10
5961
7484
3144
4636
5282
5708
5875
8390
3322
5223
7975
197
4653
8283
598
5393
8624
906
7249
7542
1223
2148
8195
976
2001
5005
wherein
letting b i denote a bit in the i th sequence of bits before the permutation (for i=0, 1, . . . 7), and
letting v i denote a bit in the i th sequence of bits after the permutation (for i=0, 1, . . . 7),
the predetermined permutation rule is:
v 0 =b 2 , v 1 =b 6 , v 2 =b 0 , v 3 =b 1 , v 4 =b 4 , v 5 =b 5 , v 6 =b 3 , v 7 =b 7 .