IP Library Granted Patent US 9,247,231
Granted Patent B2
US 9,247,231 · App. 14/129,482 · Granted Jan 26, 2016

3D image signal processing apparatus

Inventor: Shigeo Hamamura (Tokyo, JP)
Assignee: NEC DISPLAY SOLUTIONS, LTD.
H04N13/004H04N13/0048H04N13/0059H04N13/0497
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Quick Facts
Patent No.
US 9,247,231
App. No.
14/129,482
Granted
Jan 26, 2016
Kind
B2
Abstract

In 3D display, when double the frequency of the input clock exceeds the maximum rate of transmission to cinema display circuit 104 , the multiply ratio of the clock is lowered from 2× multiplication and the output horizontal total clock number is reduced accordingly.

Claims (11)

1. A 3D image signal processing apparatus which,

receives a plurality of image signals for the left eye and the right eye, each image signal including a clock signal and each image signal representing a plurality of lines,

outputs one frame of output image signals formed by combining one line of the left-eye image signal and one line of the right-eye image signal, alternately, to a display circuit, and

causes the display circuit to display images of every frame,

the apparatus comprising:

a first line storing unit storing every line of the left-eye image;

a second line storing unit storing every line of the right-eye image;

a measuring unit measuring the frequency of the clock signal in the input left-eye image signal or right-eye image signal; and,

a control unit which, when the frequency of the clock signal measured by the measuring unit is higher than a permissible maximum transmission rate for the display circuit,

sets the frequency of the clock signal for output image signals, which are to be used for reading out one line of the left-eye image signal and one line of the right-eye image signal from the first line storing unit and the second line storing unit respectively, to be smaller than double the frequency of the clock signal in the input signal, and

reduces the number of clock signals for output image signals that are included in the horizontal period in the output image signal, to less than the number of clock signals that are included in the horizontal period of the input signal.

Assignments (2)
CHANGE OF NAME Recorded Feb 8, 2021
From: NEC DISPLAY SOLUTIONS, LTD.
To: SHARP NEC DISPLAY SOLUTIONS, LTD.
Reel/Frame 055256/0755 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2013
From: HAMAMURA, SHIGEO
To: NEC DISPLAY SOLUTIONS, LTD.
Reel/Frame 032094/0351 →
Continuity (1)
Related Publication 20140146138A1 · May 29, 2014