IP Library Granted Patent US 9,012,914
Granted Patent B2
US 9,012,914 · App. 14/130,941 · Granted Apr 21, 2015

Thin-film transistor and method for manufacturing thin-film transistor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,012,914
App. No.
14/130,941
Granted
Apr 21, 2015
Kind
B2
Abstract

A method for manufacturing a thin-film transistor includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode which are opposed to each other and each of which has at least a portion located above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and performing, in a hydrogen atmosphere, plasma treatment on an altered layer which (i) is a surface layer of the protective layer exposed from the source electrode and the drain electrode and altered by the dry etching, and (ii) has at least a portion contacting a surface of the semiconductor layer.

Claims (74)

1. A thin-film transistor, comprising:

a gate electrode above a substrate;

a gate insulating layer above the gate electrode;

a semiconductor layer that is opposed to the gate electrode with the gate insulating layer therebetween;

an etch-stopper layer above the semiconductor layer and comprising an organic material; and

a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer,

wherein the etch-stopper layer includes a modified layer in a region which (i) is in a surface of the etch-stopper layer exposed from the source electrode and the drain electrode and (ii) has at least a portion contacting a surface of the semiconductor layer, the modified layer being an altered layer that has been modified, the altered layer being generated by alteration of a material of the etch-stopper layer, and

wherein the modified layer has a chlorine concentration which is at least ten times higher than a chlorine concentration of the etch-stopper layer.

2. The thin-film transistor according to claim 1 ,

wherein the altered layer is a surface layer of the etch-stopper layer altered by dry etching performed to pattern the semiconductor layer.

3. The thin-film transistor according to claim 1 ,

wherein the modified layer has a thickness of at least 30 nm.

4. A thin-film transistor, comprising:

a gate electrode above a substrate;

a gate insulating layer above the gate electrode;

a semiconductor layer that is opposed to the gate electrode with the gate insulating layer therebetween;

an etch-stopper layer above the semiconductor layer and comprising an organic material; and

a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer,

wherein the etch-stopper layer includes a modified layer in a region which (i) is in a surface of the etch-stopper layer exposed from the source electrode and the drain electrode and (ii) has at least a portion contacting a surface of the semiconductor layer, the modified layer being an altered layer that has been modified, the altered layer being generated by alteration of a material of the etch-stopper layer, and

wherein the modified layer has a carbon concentration which is at most one hundredth of a carbon concentration of the etch-stopper layer.

5. A thin-film transistor, comprising:

a gate electrode above a substrate;

a gate insulating layer above the gate electrode;

a semiconductor layer that is opposed to the gate electrode with the gate insulating layer therebetween;

an etch-stopper layer above the semiconductor layer and comprising an organic material; and

a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer,

wherein the etch-stopper layer includes a modified layer in a region which (i) is in a surface of the etch-stopper layer exposed from the source electrode and the drain electrode and (ii) has at least a portion contacting a surface of the semiconductor layer, the modified layer being an altered layer that has been modified, the altered layer being generated by alteration of a material of the etch-stopper layer, and

wherein the altered layer has a density higher than a density of a portion of the etch-stopper layer which is not altered by the dry etching.

6. A method for manufacturing a thin-film transistor, the method comprising:

preparing a substrate;

forming a gate electrode above the substrate;

forming a gate insulating layer above the gate electrode;

forming a semiconductor film above the gate insulating layer;

forming, above the semiconductor film, an etch-stopper layer comprising an organic material;

forming a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer;

performing dry etching to (i) form, from the semiconductor film, a semiconductor layer, and (ii) form an altered layer by altering a surface layer of the etch-stopper layer exposed from the source electrode and the drain electrode, the altered layer having at least a portion contacting a surface of the semiconductor layer; and

performing plasma treatment on the altered layer in a hydrogen atmosphere.

7. A method for manufacturing a thin-film transistor, the method comprising:

preparing a substrate;

forming a gate electrode above the substrate;

forming a gate insulating layer above the gate electrode;

forming a semiconductor film above the gate insulating layer;

forming, above the semiconductor film, an etch-stopper layer comprising an organic material;

forming a source electrode and a drain electrode that are opposed to each other, each of the source electrode and the drain electrode having at least a portion located above the etch-stopper layer;

forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and

performing plasma treatment on an altered layer in a hydrogen atmosphere, the altered layer being a surface layer of the etch-stopper layer that is (i) exposed from the source electrode and the drain electrode and (ii) altered by the dry etching, the altered layer having at least a portion contacting a surface of the semiconductor layer,

wherein in the performing of plasma treatment on an altered layer, a parallel-plate electrode radio frequency (RF) plasma apparatus is used.

8. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a density higher than a density of a portion of the etch-stopper layer which is not altered by the dry etching.

9. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a thickness of at least 30 nm.

10. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a chlorine concentration which is at least ten times higher than a chlorine concentration of the etch-stopper layer.

11. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the altered layer has a carbon concentration which is at most one hundredth of a carbon concentration of the etch-stopper layer.

12. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein in the performing of plasma treatment on an altered layer, the substrate is set to a temperature of at least 280 degrees Celsius and at most 350 degrees Celsius to generate plasma.

13. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein in the performing of plasma treatment on an altered layer, a distance between parallel-plate electrodes of the parallel-plate electrode RF plasma apparatus is at least 500 mm and at most 600 mm.

14. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the semiconductor film is an oxide semiconductor film.

15. The method for manufacturing the thin-film transistor according to claim 7 ,

wherein the semiconductor film is a silicon film.

16. The method for manufacturing the thin-film transistor according to claim 15 , further comprising:

performing plasma treatment as a first plasma treatment on the semiconductor film in a hydrogen atmosphere, before the forming of an etch-stopper layer,

wherein the performing of plasma treatment on an altered layer is performed as a second plasma treatment.

17. The method for manufacturing the thin-film transistor according to claim 16 ,

wherein the first plasma treatment is a process in which a dangling bond of a silicon element in the silicon film is hydrogen-terminated, and

the second plasma treatment is a process in which the altered layer is modified to equalize an amount of fixed charges in the altered layer and in a portion other than the altered layer in the etch-stopper layer.

18. The method for manufacturing the thin-film transistor according to claim 16 ,

wherein the second plasma treatment generates plasma having an intensity lower than an intensity of plasma generated by the first plasma treatment.

19. The method for manufacturing the thin-film transistor according to claim 18 ,

wherein each of the first plasma treatment and the second plasma treatment uses a parallel-plate electrode radio frequency (RF) plasma apparatus, and

a distance between parallel-plate electrodes of the parallel-plate electrode RF plasma apparatus is greater in the second plasma treatment than in the first plasma treatment.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2014
From: KISHIDA, YUJI; NISHIDA, KENICHIROU; MATSUMOTO, MITSUTAKA
To: PANASONIC CORPORATION
Reel/Frame 032421/0304 →