IP Library Patent Application 14132596
Patent Application
App. No. 14/132,596

Modular Analog Frontend

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Quick Facts
Patent No.
US None
App. No.
14/132,596
Abstract

A system may include a first stage comprising first signaling components for a first protocol, and a second stage comprising second signaling components for the first protocol and a second protocol. The system may further include logic configured to receive an incoming data stream, and determine a stream protocol for the data stream. The logic may be further configured to, responsive to the determination, activate the at least a portion of the first stage when the stream protocol is compliant with the first protocol, and when the stream protocol is compliant with the second protocol, deactivate the first stage.

Claims (58)

1 . A device comprising;

a first stage comprising first signaling components for a first protocol and a second protocol;

a second stage comprising second signaling components for the first protocol; and

logic configured to:

receive an incoming data stream;

determine a stream protocol for the data stream; and

responsive to the determination:

when the stream protocol is compliant with the first protocol, activate the at least a portion of the second stage; and

when the stream protocol is compliant with the second protocol, deactivate the second stage.

2 . The device of claim 1 , further comprising a bypass circuit configured to bypass the second stage when activated.

3 . The device of claim 2 , where the logic is further configured to activate the bypass when the stream protocol is compliant with the second protocol.

4 . The device of claim 1 , where:

the first signaling components comprise a first converter element configured to produce a first set of bits based on the data stream; and

the second signaling components comprise a second converter element configured to produce a second set of bits based on the data stream.

5 . The device of claim 4 , where:

the first set of bits is compliant with the first and second protocols; and

the second set of bits is compliant with the first protocol.

6 . The device of claim 1 , where:

the first signaling components comprise a first amplifier configured to amplify the data stream at a first level; and

the second signaling components comprise a second amplifier configured to amplify the data stream at a second level.

7 . The device of claim 6 , where the second level is greater than the first level.

8 . The device of claim 6 , where the second amplifier is configured to amplify the data stream after amplification via the first amplifier.

9 . The device of claim 6 , where the second amplifier is configured to amplify the data stream to a second power level via amplification from an incoming power level of the data stream.

10 . The device of claim 1 , where:

the first protocol is configured to operate at a first bit rate; and

the second protocol is configured to operate at a second bit rate different from the first.

11 . The device of claim 10 , where the logic is further configured to determine a stream bit rate of the data stream to determine the stream protocol.

12 . The device of claim 1 , where the logic is further configured to:

receive the data stream over an input cable;

determine a cable length for the input cable; and

responsive to the determination of the cable length, forgo activation of an amplifier of the second signaling components when the stream protocol is compliant with the second protocol.

13 . A method, comprising:

receiving, at a frontend, a data stream;

determining that the data stream is compliant with a first protocol;

activating a first stage of the frontend, the first stage compliant with the first protocol and a second protocol; and

bypassing a second stage of the frontend, the second stage compliant with the second protocol.

14 . The method of claim 13 , where determining that the data stream is compliant with the first protocol comprises determining a bit rate of the data stream.

15 . The method of claim 13 , where bypassing the second stage comprises bypassing a converter element configured to generate a set of bits compliant with the second protocol.

16 . The method of claim 13 , where:

the first protocol comprises a IEEE 40GBASE-T compliant protocol; and

the second protocol comprises a IEEE 10GBASE-T compliant protocol.

17 . The method of claim 13 , where bypassing comprises changing an input amplifier of the frontend from a second amplifier of the second stage to a first amplifier of the first stage.

18 . The method of claim 17 , where bypassing comprises activating a bypass network to maintain an input parameter of the frontend.

19 . A device, comprising:

a frontend comprising:

a first amplifier stage configured to amplify an incoming data signal at a first level, the first level being compliant with a first protocol;

a second amplifier stage configured to amplify the incoming data signal at a second level, the second level being compliant with a second protocol;

a first converter element configured to generate a first set bits based on the incoming signal, the first set of bits compliant with the first and second protocols; and

a second converter element configured to generate a second set of bits based on the incoming signal, the second set of bits compliant with the second protocol; and

logic, in operative communication with the frontend, the logic configured to:

determine a stream protocol for the incoming signal; and

responsive to the determination:

when the stream protocol is compliant with the second protocol, activate the second amplifier stage and the second converter element; and

when the stream protocol is compliant with the first protocol, deactivate the second amplifier stage and the second converter element.

20 . The device of claim 19 , where:

the first protocol is configured to operate at a first bit rate;

the second protocol is configured to operate at a second bit rate different from the first; and

the logic further configured to determine the stream protocol based on the bit rate of the stream.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2013
From: VECCHI, DAVIDE; MULDER, JAN; VAN DER GOES, FRANCISCUS MARIA LEONARDUS; ARSLAN, EROL; GRIMWOOD, MICHAEL RANDALL
To: BROADCOM CORPORATION
Reel/Frame 031810/0743 →