Counting circuit of semiconductor device and duty correction circuit of semiconductor device using the same

1. A duty correction circuit of a semiconductor device, comprising:

a duty cycle error detection unit configured to detect a duty cycle error of a source clock;

a plurality of counting units configured to count respective bits of duty correction codes in response to a plurality of counting clocks, respectively, and a counting direction of the plurality of counting units is controlled in response to an output signal of the duty cycle error detection unit;

a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and

a duty cycle control unit configured to control a duty cycle of the source clock in response to the duty correction codes.

2. The duty correction circuit of claim 1 , wherein the plurality of counting units respectively count the plurality of bits included in the duty correction codes in one-to-one correspondence to toggling of the plurality of counting clocks.

3. The duty correction circuit of claim 2 , wherein the plurality of counting units respectively perform counting operations by combining carry information between adjoining units.

4. The duty correction circuit of claim 1 ,

wherein the clock toggling control unit determines the number of counting clocks to toggle in an initial operation among the plurality of counting clocks, according to values of the clock control signals that are set in the initial operation,

wherein, during a period in which the output signal of the duty cycle error detection unit is deactivated after the initial operation, the clock toggling control unit sequentially toggles counting clocks that have not toggled among the plurality of counting clocks, and

wherein, during a period in which the output signal of the duty cycle error detection unit is activated after the initial operation, the clock toggling control unit toggles all of the plurality of counting clocks.

5. The duty correction circuit of claim 4 , wherein the clock toggling control unit comprises:

a toggling operation control signal generation part configured to generate a plurality of toggling operation control signals,

wherein the plurality of toggling operation control signals, in the initial operations of the respective toggling operation control signals, are sequentially activated by the toggling operation control signal generation part starting from a deactivated signal each time a source clock toggles during the period in which the output signal of the duty cycle error detection unit is deactivated in response to the clock control signals;

wherein the plurality of toggling operation control signals, in the initial operations of the respective toggling operation control signals, are all activated by the toggling operation control signal generation part during the period in which the output signal of the duty cycle error detection unit is activated;

wherein the toggling operation control signal generation part determines whether or not to activate the plurality of toggling operation control signals in response to the clock control signals; and

a plurality of counting clock generation parts configured to generate the plurality of counting clocks in response to the respective toggling operation control signals and the source clock.

6. The duty correction circuit of claim 5 , wherein the toggling operation control signal generation part comprises:

an initialization determining section configured to control the number of toggling operation control signals to be initialized to a deactivated state among the plurality of toggling operation control signals in response to the clock control signals and a reset signal; and

an activation control section configured to sequentially activate at least one toggling operation control signals in the deactivated state among the plurality of toggling operation control signals each time toggling of the source clock is repeated at least one time during the period in which the output signal of the duty cycle error detection unit is deactivated, and activate all of the plurality of toggling operation control signals during the period in which the output signal of the duty cycle error detection unit is activated.

7. The duty correction circuit of claim 1 ,

wherein the clock toggling control unit determines the number of counting clocks to toggle in an initial operation among the counting clocks, according to values of the clock control signals which are set in the initial operation, and

wherein, after the initial operation, the clock toggling control unit sequentially toggles counting clocks having not toggled among the plurality of counting clocks, and toggles all the plurality of counting clocks from a time an operation defined number of counting clocks toggle.

8. The duty correction circuit of claim 7 , wherein the clock toggling control unit comprises:

a toggling operation control signal generation part configured to generate a plurality of toggling operation control signals;

wherein the plurality of toggling operation control signals, in initial operations of the respective toggling operation control signals, are sequentially activated by the toggling operation control signal generation part starting from a deactivated signal each time a source clock toggles;

wherein all of the plurality of toggling operation control signals, in the initial operations of the respective toggling operation control signals, are activated when the number of activated toggling operation control signals is equal to or greater than an operation defined number in response to the clock control signals

wherein the toggling operation control signal generation part determines in terms of whether or not to activate the plurality of toggling operation control signals in response to the clock control signals; and

a plurality of counting clock generation parts configured to generate the plurality of counting clocks in response to the respective toggling operation control signals and the source clock.

9. The duty correction circuit of claim 8 , wherein the toggling operation control signal generation part comprises:

an initialization determining section configured to control the number of toggling operation control signals to be initialized to a deactivated state, among the plurality of toggling operation control signals in response to the clock control signals and a reset signal; and

an activation control section configured to sequentially activate at least one toggling operation control signals in the deactivated state among the plurality of toggling operation control signals each time toggling of the source clock is repeated at least one time, and activate all of the plurality of toggling operation control signals when the number of toggling operation control signals activated among the plurality of toggling operation control signals is equal to or greater than the operation defined number.

10. The duty correction circuit of claim 5 , wherein the plurality of counting clock generation parts toggle and output the respective counting clocks in correspondence to toggling of the source clock when the respective toggling operation control signals are applied in an activated state, and maintain the respective counting clocks outputted in a deactivated state regardless of toggling of the source clock when the respective toggling operation control signals are applied in a deactivated state.

11. The duty correction circuit of claim 5 , wherein the respective values of the plurality of toggling operation control signals are changed in synchronization with an edge of the source clock.

12. The duty correction circuit of claim 1 ,

wherein the duty cycle error detection unit detects when a period in which the source clock is deactivated is longer than a period in which the source clock is activated, deactivates the output signal, and thereby sets a counting direction of the counting units to an increasing direction, and

wherein the duty cycle error detection unit detects when the period in which the source clock is deactivated is shorter than the period in which the source clock is activated, activates the output signal, and thereby sets the counting direction of the plurality of counting units to a decreasing direction.

13. The duty correction circuit of claim 1 , wherein the duty cycle control unit controls the duty cycle of the source clock by a larger amount in correspondence to a changed value of a bit nearer to a most significant bit among the duty correction codes than in correspondence to a changed value of a bit nearer to a least significant bit among the duty correction codes.