Integrated circuit comprising a clock tree cell

1. Integrated circuit, comprising:

a semiconductor substrate lying essentially in a plane called the substrate plane;

a first semiconductor well lying in a plane called the well plane parallel to the substrate plane;

a plurality of standard cells placed next to one another, each standard cell comprising a first field-effect transistor in FDSOI technology, the first transistor comprising a first semiconductor ground plane located immediately on the first well so as to make electrical contact with the first well, the first well thus being common to all the standard cells placed next to one another;

a clock tree cell contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, the second transistor comprising a second semiconductor ground plane located immediately on the first well so as to form a p-n junction with this first well, this second ground plane having, for this purpose, an opposite doping type to the doping of the first well; and

an electrical power supply network able to apply separate electrical biases directly to the first and second ground planes.

2. Circuit according to claim 1 , in which the circuit comprises a power source adapted to be electrically connected to the electrical power supply network and able to apply separate electrical biases to the first and second ground planes.

3. Circuit according to claim 1 , in which the clock tree cell comprises a trench isolation ( 45 ), made of an electrically insulating material, encircling the second ground plane in a plane parallel to the substrate plane.

4. Circuit according to claim 1 , in which each standard cell and clock tree cell comprises, for each ground plane of this cell, at least one first connector adapted to make direct electrical contact with said ground plane, this first connector being able to electrically bias said ground plane with an electrical bias delivered by an external voltage source.

5. Circuit according to claim 1 , in which each ground plane of each transistor of the clock cell has an opposite doping type to the doping of the well on which this transistor is located.

6. Circuit according to claim 5 , in which:

the circuit comprises a second semiconductor well contiguous with the first well and extending parallel to the first well in the well plane, the second well having an opposite doping type to the doping of the first well;

each standard cell includes a third field-effect transistor in FDSOI technology, this third transistor comprising a third ground plane located immediately on the second well so as to make electrical contact with this second well, the second well thus being common to all the standard cells placed next to one another on the first well, the first and third ground planes having the same doping type as the doping of the first and second wells, respectively; and

the clock tree cell includes a fourth field-effect transistor in FDSOI technology, this fourth transistor comprising a fourth ground plane located immediately above the second well so as to form a p-n junction with this second well, this fourth ground plane having an opposite doping type to the doping of the second well.

7. Circuit according to claim 1 , in which:

the first ground plane has the same doping type as the doping of the first well;

each standard cell includes a third field-effect transistor in FDSOI technology, this third transistor comprising a third ground plane located immediately on the first well so as to make electrical contact with this first well, the third ground plane having an opposite doping type to the doping of the first ground plane, the first well thus being common to all the transistors of the standard cells placed next to one another on the same first well;

the clock tree cell includes a fourth field-effect transistor in FDSOI technology, the fourth transistor comprising a fourth ground plane located immediately above the first well so as to form a p-n junction with this first well, this fourth ground plane having, for this purpose, the same doping type as the second and third ground planes.

8. Circuit according to claim 7 , in which the second and fourth ground planes of the clock tree cell make electrical contact with each other, so that it is possible to bias these second and fourth ground planes with one and the same electrical potential by applying an electrical bias to only one of these second and fourth ground planes.

9. Circuit according to claim 1 , in which:

each standard cell includes a third field-effect transistor in FDSOI technology, this third transistor comprising a third ground plane located immediately above the first well so as to make electrical contact with this first well, the first well thus being common to all the transistors of the standard cells placed next to one another on the same first well, the third ground plane having an opposite doping type to the doping of the first ground plane; and

the clock tree cell includes a fourth field-effect transistor in FDSOI technology, this fourth transistor comprising a fourth ground plane located immediately above the first well so as to make electrical contact with this first well, and having an opposite doping type to the doping of the second ground plane.

10. Circuit according to claim 1 , in which:

the circuit comprises a second well contiguous with the first well and having an opposite doping type to the doping of the first well;

the standard cell includes a third field-effect transistor in FDSOI technology, the third transistor comprising a third ground plane located immediately above the second well so as to make electrical contact with this second well, and having an opposite doping type to the doping of the first ground plane; and

the clock tree cell includes a fourth field-effect transistor in FDSOI technology, this fourth transistor comprising a fourth ground plane located immediately above the second well so as to make electrical contact with this second well, and having the same doping type as the doping of the second ground plane.

11. Circuit according to claim 1 , in which the circuit comprises a plurality of rows of cells placed parallel to one another on the substrate, each row including at least one example of the first well and a plurality of standard cells, which cells are placed next to one another in this row, one of these rows, called the middle row, comprising the clock tree cell contiguous with the standard cells.

12. Method for using an integrated circuit, comprising the following steps:

providing an integrated circuit according claim 1 ;

applying a first electrical bias to the first ground plane;

applying a second electrical bias to the second ground plane, the second bias being chosen depending on the first electrical bias applied at the same time to the first ground plane, so as to reverse bias the p-n junction formed between the second ground plane and the first well.