Semiconductor device

1. A semiconductor device, comprising:

a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad;

a first N-type diffusion region that is formed on the P-type semiconductor substrate and is connected to the pad;

a region of an internal circuit that is formed on the P-type semiconductor substrate; and

a minority carrier capture region formed between the first N-type diffusion region and the region of the internal circuit, for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad,

the minority carrier capture region including a triple guard ring including:

a first P-type diffusion region;

a second P-type diffusion region; and

a second N-type diffusion region that is located between the first P-type diffusion region and the second P-type diffusion region,

the first P-type diffusion region and the second P-type diffusion region each being connected to the ground pad respectively through metal film wirings that are separately formed, and

the second N-type diffusion region being connected to the power supply pad,

wherein the separately formed metal wirings comprise a first metal film wirings to which the first P-type diffusion region is electrically connected and a second metal film wiring wired independently from the first metal film wiring and to which the second P-type diffusion region is electrically connected, each of the first and second metal film wirings being electrically connected to the ground pad.

2. A semiconductor device according to claim 1 , further comprising an NMOS transistor that functions as an ESD protection circuit, the NMOS transistor including a source and a gate connected to the ground pad and a drain as an N-type diffusion region connected to the pad.

3. A semiconductor device according to claim 1 , further comprising an open-drain output PMOS transistor including a source connected to the power supply pad and a drain as a P-type diffusion region connected to the pad.

4. A semiconductor device according to claim 1 , further comprising an open-drain output NMOS transistor including a source connected to the ground pad and a drain as an N-type diffusion region connected to the pad.

5. A semiconductor device according to claim 1 , wherein the minority carrier capture region further includes an N-type diffusion regions; and wherein the second N-type diffusion region is formed in a surface of the N-type well.

6. A semiconductor device comprising:

a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad;

a first N-type diffusion region formed on the P-type semiconductor substrate and connected to the pad;

an internal circuit region formed on the P-type semiconductor substrate; and

a minority carrier capture region formed between the first N-type diffusion region and the internal circuit region for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad, the minority carrier capture region including a first P-type diffusion region, a second P-type diffusion region, and a second N-type diffusion region connected to the power supply pad and located between the first P-type diffusion region and the second P-type diffusion region, the first P-type diffusion region and the second P-type diffusion region being connected to the ground pad through separately formed metal wirings arranged so as to avoid mutual contact with one another, the separately formed metal wirings comprising a first metal film wiring to which the first P-type diffusion region is electrically connected and a second metal film wiring wired independently from the first metal film wiring and to which the second P-type diffusion region is electrically connected, each of the first and second metal film wirings being electrically connected to the ground pad.

7. A semiconductor device according to claim 6 , wherein the minority carrier capture region forms a guard ring between the first N-type diffusion region and the internal circuit region, the triple guard ring including the first P-type diffusion region, the second P-type diffusion region, and the second N-type diffusion region.

8. A semiconductor device according to claim 7 , wherein pad, the ground pad, the power supply pad, and the protection circuit are formed outside the guard ring.

9. A semiconductor device according to claim 6 , wherein the minority carrier capture region further includes an N-type well located between the first and second P-type diffusion regions; and wherein the second N-type diffusion region is formed on a surface of the N-type well.

10. A semiconductor device according to claim 6 , further comprising an NMOS transistor that functions as an ESD protection circuit, the NMOS transistor including a source and a gate connected to the ground pad and a drain as an N-type diffusion region connected to the pad.

11. A semiconductor device according to claim 6 , further comprising an open-drain output PMOS transistor including a source connected to the power supply pad and a drain as a P-type diffusion region connected to the pad.

12. A semiconductor device according to claim 6 , further comprising an open-drain output NMOS transistor including a source connected to the ground pad and a drain as a N-type diffusion region connected to the pad.