Air-gap forming techniques for interconnect structures
An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.
1. An interconnect structure comprising:
a first low-k dielectric layer formed over a substrate;
a first metal line disposed in the first low-k dielectric layer, wherein the first metal line comprises a first conductive body with a first width and an up landing pad with a second width; wherein the first width is smaller than the second width;
a first air-gap adjacent to sidewalls of the first conductive body;
a second low-k dielectric layer formed over the first low-k dielectric layer; and
a first via in the second low-k dielectric layer and disposed on the up landing pad.
2. The interconnect structure of claim 1 , wherein the up landing pad has outer sidewalls that abut the first low-k dielectric layer.
3. The interconnect structure of claim 1 , further comprising:
a down landing pad in the first low-k dielectric layer and arranged in a common horizontal plane with the first metal line; and
a second via disposed under the down landing pad and electrically coupled to a lower surface of the down landing pad;
wherein a second air-gap is adjacent to sidewalls of the down landing pad.
4. The interconnect structure of claim 3 , wherein the down landing pad has the first width.
5. The interconnect structure of claim 1 , wherein the first metal line comprises a copper core having a barrier layer abutting outer lateral sidewalls thereof and further comprises a Cobalt cap layer over an upper surface thereof.
6. The interconnect structure of claim 5 , wherein the barrier layer comprises Tantalum (Ta), Tantalum Nitride (TaN), Cobalt(Co), or alloy thereof.
7. A semiconductor device comprising:
a first low-k dielectric layer over a substrate; and
a first conductive layer in the first low-k dielectric layer comprising a down landing pad and a up landing pad that are arranged in a common horizontal plane, wherein the down landing pad and the up landing pad each include outer sidewalls;
wherein the down landing pad of the first conductive layer has an air-gap between its outer sidewalls and the first low-k dielectric layer;
wherein the up landing pad of the first conductive layer has its sidewalls adjacent to the first low-k dielectric layer without air-gaps being formed between the outer sidewalls of the up landing pad and the first low-k dielectric layer.
8. The semiconductor device of claim 7 , further comprising:
a second low-k dielectric layer over the first low-k dielectric layer; and
a first via in the second low-k dielectric layer and vertically aligned to the up landing pad of the first conductive layer.
9. The semiconductor device of claim 8 , wherein the first via is disposed on the up landing pad of the first conducive layer and connected to a second conductive layer over the second low-k dielectric layer.
10. The semiconductor device of claim 7 , wherein the down landing pad or the up landing pad of the first conductive layer is connected to a third conductive layer under the first low-k dielectric layer or a device disposed on the substrate.
11. A semiconductor device comprising:
a first low-k dielectric layer disposed over a substrate;
a first landing pad and a second landing pad arranged in a common horizontal plane within the first low-k dielectric layer;
a second low-k dielectric layer disposed over the first low-k dielectric layer;
a first via disposed within the second low-k dielectric layer and contacting the second landing pad; and
an air-gap disposed along sidewalls of the first landing pad and abutting the first low-k dielectric layer;
wherein the second landing pad has sidewalls adjacent to the first low-k dielectric layer without air-gaps being formed between the sidewalls of the second landing pad and the first low-k dielectric layer.
12. The semiconductor device of claim 11 , wherein the air-gap has a height that is equal to a height of the first landing pad.
13. The semiconductor device of claim 11 , wherein the first via is connected to a second conductive layer over the second low-k dielectric layer.
14. The semiconductor device of claim 11 , wherein the first landing pad is connected to a third conductive layer under the first low-k dielectric layer through a second via disposed within the first low-k dielectric layer.
15. The semiconductor device of claim 11 , wherein the first landing pad has a width smaller than that of the second landing pad.
16. The semiconductor device of claim 11 , wherein a first trench where the first landing pad and the air-gap are disposed has a first width that is equal to a second width of a second trench where the second landing pad is disposed.
17. The semiconductor device of claim 11 , wherein the first landing pad and the second landing pad are electrically connected.
18. The semiconductor device of claim 11 , wherein the first landing pad comprises a copper core having a barrier layer covering the sidewalls and further comprises a cobalt cap layer covering a top surface.
19. The semiconductor device of claim 18 , wherein the barrier layer comprises Tantalum (Ta), Tantalum Nitride (TaN), Cobalt(Co), or alloy thereof.
20. The semiconductor device of claim 11 , wherein the second landing pad comprises a copper core having a barrier layer covering the sidewalls and further comprises a cobalt cap layer covering a bottom surface.