IP Library Granted Patent US 9,496,861
Granted Patent B2
US 9,496,861 · App. 14/139,104 · Granted Nov 15, 2016

Multiplexer for voltage measurement and voltage measuring unit including the same

Inventors: Kazuhiro Shimomura (Osaka, JP); Ryouta Akeyama (Kanagawa, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H03K17/005G01R1/206G01R19/2503G01R31/362G01R31/3658
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Quick Facts
Patent No.
US 9,496,861
App. No.
14/139,104
Granted
Nov 15, 2016
Kind
B2
Abstract

A multiplexer for voltage measurement includes: a first switch disposed on a first channel extending between at least one high-voltage input terminal and an output terminal; a plurality of second switches respectively disposed on second channels each extending between each of input terminals other than the high-voltage input terminal and the output terminal; and a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch. Each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage.

Claims (35)

1. A multiplexer for voltage measurement configured to receive voltages at connection terminals of a plurality of battery cells connected in series and constituting a battery cell array and output one of the voltages, to measure voltages of the battery cells,

the multiplexer comprising:

a plurality of input terminals to which the voltages at the connection terminals of the plurality of battery cells are respectively input;

an output terminal through which any one of the voltages input from the plurality of input terminals is output;

a first switch disposed on a first channel extending between at least one high-voltage input terminal that is one of the plurality of input terminals and the output terminal and configured to establish or cut a connection between the high-voltage input terminal and the output terminal, the high-voltage input terminal being connected to a predetermined number of battery cells, the predetermined number being counted from a side where a highest voltage among the voltages respectively applied to the plurality of input terminals is applied;

a plurality of second switches respectively disposed on second channels each extending between each of the input terminals other than the high-voltage input terminal and the output terminal so as to respectively correspond to the input terminals, and configured to selectively establish or cut a connection between any one of the input terminals other than the high-voltage input terminal and the output terminal; and

a third switch disposed between a group of the plurality of second switches and an output terminal side end of the first switch, wherein

each of the first switch and the third switch is configured to operate even by a voltage higher than a power supply voltage that is based on a voltage of the battery cell array, the voltage of the battery cell array being used to drive each of the first, second, and third switches.

2. The multiplexer according to claim 1 , wherein the high-voltage input terminal is the input terminal to which a highest voltage among the voltages respectively applied to the plurality of input terminals is applied.

3. The multiplexer according to claim 1 , wherein:

the output terminal is constituted by a pair of output terminals; and

each of the first switch, the second switches, and the third switch includes

a normal phase switch configured to establish or cut a connection between any one of the plurality of input terminals and one of the pair of output terminals, and

a reverse phase switch configured to establish or cut a connection between any one of the plurality of input terminals and the other of the pair of output terminals.

4. The multiplexer according to claim 1 , wherein the first switch includes:

a first MOS transistor in which a first main terminal thereof is connected to the input terminal, and a second main terminal thereof is connected to the output terminal;

a first constant voltage element connected between a control terminal of the first MOS transistor and the first main terminal thereof and configured to define a maximum value of a potential difference between the control terminal and the first main terminal;

a first capacitor including one end connected to the control terminal;

a fourth switch configured to establish or cut a connection between the first capacitor and a reference potential; and

a first constant voltage circuit configured to apply a predetermined voltage to between the first capacitor and the fourth switch.

5. The multiplexer according to claim 4 , wherein the first constant voltage circuit includes:

a second constant voltage element connected to the other end of the first capacitor; and

a current source configured to supply a current to the second constant voltage element to apply a predetermined constant voltage to between the first capacitor and the second constant voltage element.

6. The multiplexer according to claim 4 , wherein the third switch includes:

a second MOS transistor in which a first main terminal thereof is connected to the second switches, and a second main terminal thereof is connected to the output terminal, the second MOS transistor being complementary to the first MOS transistor;

a third constant voltage element connected between a control terminal of the second MOS transistor and the first main terminal thereof and configured to define a maximum value of a potential difference between the control terminal and the first main terminal;

a second capacitor including one end connected to the control terminal;

a fifth switch configured to establish or cut a connection between the second capacitor and a reference potential; and

a second constant voltage circuit configured to apply a predetermined voltage to between the second capacitor and the fifth switch.

7. The multiplexer according to claim 3 , comprising:

a pair of sixth switches, one of which is connected between the first switch and one of the pair of output terminals, and the other of which is connected between the third switch and the other of the pair of output terminals; and

a flying capacitor connected between the first switch and one of the pair of sixth switches and between the third switch and the other of the pair of sixth switches.

8. A voltage measuring unit comprising:

the multiplexer according to claim 1 ; and

a signal processor configured to perform calculation processing of voltages of the battery cells based on the voltages at the input terminals output from the pair of output terminals.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2014
From: SHIMOMURA, KAZUHIRO; AKEYAMA, RYOUTA
To: PANASONIC CORPORATION
Reel/Frame 032360/0167 →
Priority Claims (1)
JP 2011-143209 · Jun 28, 2011 · national
Continuity (2)
Continuation PCTJP2012001630 · Mar 9, 2012
Related Publication 20140117975A1 · May 1, 2014