IP Library Granted Patent US 9,076,959
Granted Patent B2
US 9,076,959 · App. 14/139,618 · Granted Jul 7, 2015

Manufacturing method of nonvolatile memory device and nonvolatile memory device

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Quick Facts
Patent No.
US 9,076,959
App. No.
14/139,618
Granted
Jul 7, 2015
Kind
B2
Abstract

A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.

Claims (25)

1. A method of manufacturing a non-volatile memory device comprising steps of:

forming a first electrode layer;

forming a variable resistance material layer comprising an oxygen-deficient metal oxide on the first electrode layer;

forming a second electrode layer on the variable resistance material layer;

forming a first layer on the second electrode layer;

forming, by a first lithography process, a first resist mask extending in a first direction on the first layer;

forming a first pattern extending in the first direction by etching the first layer using the first resist mask;

forming, by a second lithography process, a second resist mask extending in a second direction crossing the first direction, on the first pattern;

forming a hard mask by etching the first pattern using the second resist mask; and

forming a variable resistance element by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the hard mask such that the variable resistance element includes a second electrode, a variable resistance layer and a first electrode;

wherein a width of the second resist mask is greater than a width of the first resist mask to set a focus margin in the second lithography process greater than a focus margin in the first lithography process.

2. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the width of the first resist mask and the width of the second resist mask are 190 nm or less.

3. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the variable resistance element has a shape in which the variable resistance element includes a pair of first linear portions which are opposite to each other and a pair of second linear portions extending in a direction crossing the pair of first linear portions, when viewed from above.

4. The method of manufacturing the non-volatile memory device according to claim 1 , wherein:

in the step of forming the first pattern, the first layer is etched such that the variable resistance material layer is not exposed, and

in the step of forming the hard mask, the first pattern is etched such that the variable resistance material layer is not exposed.

5. The method of manufacturing the non-volatile memory device according to claim 1 , wherein in the step of forming the variable resistance element, at least side surfaces of the variable resistance layer are formed together.

6. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the second electrode layer comprises a precious metal.

7. The method of manufacturing the non-volatile memory device according to claim 1 , wherein when viewed from above after the step of forming the hard mask and before the step of forming the variable resistance element, the second electrode layer is exposed in a region other than the hard mask.

8. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the variable resistance material layer comprises a transition metal oxide or an aluminum oxide.

9. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the variable resistance material layer includes one selected from the group consisting of a tantalum oxide, a hafnium oxide and a zirconium oxide.

10. The method of manufacturing the non-volatile memory device according to claim 1 , wherein a ratio of the width of the second resist mask with respect to a height of the first pattern is greater than 1.

11. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the first layer includes titanium aluminum nitride.

12. The method of manufacturing the non-volatile memory device according to claim 1 , wherein the first layer includes an insulating material.

13. The method of manufacturing the non-volatile memory device according to claim 12 , wherein the first layer includes aluminum oxide.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2014
From: MURASE, HIDEAKI; ITO, SATORU; KAWASHIMA, YOSHIO; MIKAWA, TAKUMI
To: PANASONIC CORPORATION
Reel/Frame 032732/0218 →