Semiconductor device
View Patent ↗A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.
1. A semiconductor device comprising:
an extended semiconductor chip including
a first semiconductor chip and
an extension outwardly extending from a side surface of the first semiconductor chip; and
a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip,
wherein the first semiconductor chip is smaller than the second semiconductor chip,
at least one external terminal is provided on the extension, and
the plurality of bumps are placed so as not to be positioned within a transistor placement region of at least one of the first semiconductor chip or the second semiconductor chip.
2. The semiconductor device of claim 1 , wherein
a plurality of first pads are provided on part of the second semiconductor chip facing the extension,
a plurality of second pads are provided on the extension, and
the plurality of bumps include first bumps placed between the first semiconductor chip and the second semiconductor chip, and second bumps placed between the extension and the second semiconductor chip.
3. The semiconductor device of claim 2 , wherein
each first bump and each second bump have different heights.
4. The semiconductor device of claim 2 , wherein
each first bump is connected to a corresponding one of third pads provided on the first semiconductor chip,
a recess is formed in each of the first, second, and third pads,
each first bump and each second bump have different heights, and
a size of the recess in each third pad connected to a corresponding one of the first bumps is different from a size of the recess in each first pad or each second pad connected to a corresponding one of the second bumps.
5. The semiconductor device of claim 1 , wherein
a thickness of the extension is larger than that of the first semiconductor chip.
6. The semiconductor device of claim 5 , wherein
the thickness of the extension corresponds to a thickness obtained by adding the thickness of the first semiconductor chip to a distance between the first semiconductor chip and the second semiconductor chip.
7. The semiconductor device of claim 2 , wherein
each second bump disposed between the extension and the second semiconductor chip is connected to a corresponding one of the first pads of the second semiconductor chip.
8. The semiconductor device of claim 2 , wherein each second bump disposed between the extension and the second semiconductor chip is connected to a corresponding one of the second pads of the extension.
9. The semiconductor device of claim 1 , wherein
the plurality of bumps are placed within a region of at least one of the first semiconductor chip or the second semiconductor chip where a cell in which no malfunction due to a timing variation occurs is disposed, and
the cell in which no malfunction due to the timing variation occurs is at least one of an ESD protection cell, a Tie cell, a bonus cell, an area ratio adjustment cell, a power source capacity cell, an input Tie-fixed cell, or a level shifter.
10. The semiconductor device of claim 1 , wherein
at least one of the plurality of bumps is disposed within a scribe lane or a seal ring region of at least one of the first semiconductor chip or the second semiconductor chip.
11. The semiconductor device of claim 1 , wherein
at least one of the plurality of bumps is disposed within a chip corner cell region of at least one of the first semiconductor chip or the second semiconductor chip.
12. The semiconductor device of claim 1 , wherein
at least one of the plurality of bumps is disposed on a power interconnect of at least one of the first semiconductor chip or the second semiconductor chip.
13. The semiconductor device of claim 2 , wherein
the plurality of bumps include dummy bumps which do not electrically connect the extended semiconductor chip and the second semiconductor chip together, and
the dummy bumps are placed within a second region outside a first region where the first semiconductor chip and the second semiconductor chip are electrically connected together.
14. The semiconductor device of claim 13 , wherein
the dummy bumps are provided as some of the second bumps placed between the extension and the second semiconductor chip.
15. The semiconductor device of claim 13 , wherein
the dummy bumps are provided as some of the first bumps placed between the first semiconductor chip and the second semiconductor chip.
16. The semiconductor device of claim 13 , wherein
the dummy bumps are made of a non-metal material.
17. The semiconductor device of claim 1 , wherein
the extension is made of a metal material or resin.
18. The semiconductor device of claim 1 , further comprising:
a substrate on which the extended semiconductor chip and the second semiconductor chip are mounted,
wherein the substrate is bonded to a surface of the extended semiconductor chip opposite to a surface of the extended semiconductor chip bonded to the second semiconductor chip, and
the external terminal is a wire bonding pad, and is connected to the substrate through a thin metal wire.
19. The semiconductor device of claim 1 , further comprising:
a substrate on which the extended semiconductor chip and the second semiconductor chip are mounted,
wherein the substrate is bonded to a surface of the extended semiconductor chip opposite to a surface of the extended semiconductor chip bonded to the second semiconductor chip, and
the external terminal is connected to the substrate through a ball electrode.