CACHE ARCHITECTURE
A cache controller for a processing system, the cache controller being capable of providing an interface between a data requester and a plurality of memories including a first memory, a second memory and a cache memory, the cache controller being configured to, in response to receiving a request for data at a specified address in a specified memory, perform the steps of: determining whether either (a) a data field in the cache memory that corresponds to the specified address has been populated from the specified memory or (b) the specified memory is the first memory and the data field corresponding to the specified address in the cache memory has been populated from the second memory; and if that determination is positive, responding to the request by providing the content of the data field in the cache memory corresponding to the specified address.
1 . A cache controller for a processing system, the cache controller being capable of providing an interface between a data requester and a plurality of memories including a first memory, a second memory and a cache memory, the cache controller being configured to, in response to receiving a request for data at a specified address in a specified memory, perform the steps of:
determining whether either (a) a data field in the cache memory that corresponds to the specified address has been populated from the specified memory or (b) the specified memory is the first memory and the data field corresponding to the specified address in the cache memory has been populated from the second memory; and
if that determination is positive, responding to the request by providing the content of the data field in the cache memory corresponding to the specified address.
2 . A cache controller as claimed in claim 1 , wherein the first memory is a read only memory.
3 . A cache controller as claimed in claim 1 , wherein the second memory is a programmable non-volatile memory.
4 . A cache controller as claimed in claim 1 , wherein the second memory is a one-time-programmable memory.
5 . A cache controller as claimed in claim 1 , wherein the plurality of memories includes a third memory.
6 . A cache controller as claimed in claim 1 , wherein each of the plurality of memories is of a different memory technology.
7 . A cache controller as claimed in claim 1 , wherein the cache controller is implemented on a first semiconductor substrate and at least one of the first and second memories is implemented on a second semiconductor substrate.
8 . A cache controller as claimed in claim 1 , wherein the cache controller is configured to, if the said determination is negative, retrieve the content of the data field in the specified memory corresponding to the said address and respond to the request by providing the content of that data field.
9 . A cache controller as claimed in claim 1 , wherein the cache controller is configured to, if the said determination is negative, retrieve the content of the data field in the specified memory corresponding to the said address, determine whether the data field in the cache memory that corresponds to the specified address has been populated from the first or the second memories, and if that latter determination is negative populate the data field in the cache memory that corresponds to the specified address with the retrieved content of the data field in the specified memory corresponding to the said address.
10 . A data processing system comprising: a cache controller as claimed in claim 1 , the data requester, the first memory, the second memory and the cache memory.
11 . A cache controller for a processing system, the cache controller being capable of providing an interface between a data requester and a plurality of memories including a first memory, a second memory and a cache memory, the cache controller being configured to, in response to receiving a request to write data to a specified address in a specified memory, perform the steps of:
if the specified memory is the first memory, storing the data at the specified address in the first memory; and
if the data field in the cache memory that corresponds to the specified address has not been populated from the second memory, populating that data field with the data.
12 . A cache controller as claimed in claim 11 , wherein the first memory is a reprogrammable memory.
13 . A cache controller as claimed in claim 12 , wherein the second memory is a programmable non-volatile memory.
14 . A cache controller as claimed in claim 12 , wherein the second memory is a one-time-programmable memory.
15 . A cache controller as claimed in claim 12 , wherein the plurality of memories includes a third memory and the cache controller is configured to respond to at least some requests to read data from the third memory by providing data populated in the cache memory from the second memory.
16 . A data processing system comprising: a cache controller as claimed in claim 12 , the data requester, the first memory, the second memory and the cache memory.