Updating compiled native instruction paths
View Patent ↗Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.
1. A method for updating compiled native instruction paths, comprising:
interpreting a non-native instruction to generate an instruction code;
compiling the instruction code to generate a native instruction corresponding to the non-native instruction;
detecting a modification to the instruction code;
invalidating a native code fragment associated with the instruction code upon detecting the modification to the instruction code;
reinterpreting the non-native instruction to regenerate the instruction code and generate an updated instruction code; and
replacing a branch address pointed to by the modified instruction code to cause reinterpretation of the non-native instruction to regenerate the instruction code upon identifying that the modified instruction code is scheduled to be subsequently executed, wherein reinterpretation and regeneration occurs prior to subsequently executing the instruction code.
2. The method of claim 1 , further comprising:
determining if an instruction code has been regenerated; and
recompiling the updated instruction code to generate an updated native instruction corresponding to the non-native instruction, when it is determined that the instruction code has been regenerated.
3. The method of claim 1 , further comprising:
determining if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group to create a native instruction path associated with the block of instruction codes; and
recompiling the block of instruction codes as a group using the updated instruction code when it is determined that the instruction code for which a modification was detected is in the block of instruction codes.
4. The method of claim 3 , wherein the step of determining if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group comprises analyzing a quick lockup map that comprises addresses of compiled instruction codes compiled by a just-in-time compiler to identify native instruction paths that are associated with blocks of instruction codes that include the instruction code for which a modification was detected.
5. The method of claim 1 , wherein detecting a modification to the instruction code comprises determining if a valid bit associated with the instruction code indicates that the instruction code is invalid.
6. A computer program product for updating compiled native instruction paths, comprising:
a non-transitory computer-readable medium comprising:
code to interpret a non-native instruction generate an instruction code;
code to compile the instruction code to generate a native instruction corresponding to the non-native instruction;
code to detect a modification to the instruction code;
code to invalidate a native code fragment associated with the instruction code upon detecting the modification to the instruction code;
code to reinterpret the non-native instruction to regenerate the instruction code to generate an updated instruction code; and
code to replace a branch address pointed to by the modified instruction code to cause reinterpretation of the non-native instruction to regenerate the instruction code upon identifying that the modified instruction code is scheduled to be subsequently executed, wherein reinterpretation and regeneration occurs prior to subsequently executing the instruction code.
7. The computer program product of claim 6 , wherein the medium further comprises:
code to determine if an instruction code has been regenerated; and
code to recompile the updated instruction code to generate an updated native instruction corresponding to the non-native instruction when it is determined that the instruction code has been regenerated.
8. The computer program product of claim 6 , wherein the medium further comprises:
code to determine if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group to create a native instruction path associated with the block of instruction codes; and
code to recompile the block of instruction codes as a group using the updated instruction code when it is determined that the instruction code for which a modification was detected is in the block of instruction codes.
9. The computer program product of claim 8 , wherein code to determine if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group comprises code to analyze a quick lockup map that comprises addresses of compiled instruction codes compiled by a just-in-time compiler to identify native instruction paths that are associated with blocks of instruction codes that include the instruction code for which a modification was detected.
10. The computer program product of claim 6 , wherein code to detect a modification to the instruction code comprises code to determine if a valid bit associated with the instruction code indicates that the instruction code is invalid.
11. An apparatus for updating compiled native instruction paths, comprising:
a processor; and
a memory coupled to the processor, in which the processor is configured:
to interpret a non-native instruction to generate an instruction code;
to compile the instruction code to generate a native instruction corresponding to the non-native instruction;
to detect a modification to the instruction code;
to invalidate a native code fragment associated with the instruction code upon detecting the modification to the instruction code;
to reinterpret the non-native instruction to regenerate the instruction code, thereby generating an updated instruction code; and
to replace a branch address pointed to by the modified instruction code to cause reinterpretation of the non-native instruction to regenerate the instruction code upon identifying that the modified instruction code is scheduled to be subsequently executed, wherein reinterpretation and regeneration occurs prior to subsequently executing the instruction code.
12. The apparatus of claim 11 , wherein the processor is further configured:
to determine if an instruction code has been regenerated; and
to recompile the updated instruction code to generate an updated native instruction corresponding to the non-native instruction when it is determined that the instruction code has been regenerated.
13. The apparatus of claim 11 , wherein processor is further configured:
to determine if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group to create a native instruction path associated with the block of instruction codes; and
to recompile the block of instruction codes as a group using the updated instruction code when it is determined that the instruction code for which a modification was detected is in the block of instruction codes.
14. The apparatus of claim 13 , wherein the processor being configured to determine if the instruction code for which a modification was detected is part of a block of instruction codes compiled as a group comprises the processor being configured to analyze a quick lockup map that comprises addresses of compiled instruction codes compiled by a just-in-time compiler to identify native instruction paths that are associated with blocks of instruction codes that include the instruction code for which a modification was detected.
15. The apparatus of claim 11 , wherein the processor being configured to detect a modification to the instruction code comprises the processor being configured to determine if a valid bit associated with the instruction code indicates that the instruction code is invalid.