Method of driving nonvolatile semiconductor device
View Patent ↗Pulse voltages V 1 and V 2 are applied to a first upper gate electrode and a second upper gate electrode, respectively, for a period T 1 which is shorter than a period necessary to invert all the polarizations included in a ferroelectric film, while voltages Vs, Vd, and V 3 are applied to a source electrode, a drain electrode, and a lower gate electrode film, respectively, so as to increase the values of the widths WRL 1 and WRL 2 and so as to decrease the value of the width WRH. The absolute values of the pulse voltages V 1 and V 2 are smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V 3 , the pulse voltage V 1 , and the pulse voltage V 2 satisfy the following relationship: Vs, Vd, V 3 >V 1 , V 2.
1. A method for operating a nonvolatile semiconductor device, the method comprising steps of:
a step (a) of preparing the nonvolatile semiconductor device, wherein
the nonvolatile semiconductor device comprises a lower gate electrode film, a ferroelectric film, a semiconductor film, a source electrode, a drain electrode, a first upper gate electrode, and a second upper gate electrode;
the lower gate electrode film, the ferroelectric film, and the semiconductor film are stacked in this order;
the source electrode, the drain electrode, the first upper gate electrode, and the second upper gate electrode are formed on the semiconductor film;
Z direction represents a stack direction of the lower gate electrode film, the ferroelectric film, and the semiconductor film;
when viewed in a top view, the source electrode and the drain electrode face each other along X direction;
when viewed in a top view, the first upper gate electrode and the second upper gate electrode face each other along Y direction;
the X direction and the Y direction are perpendicular to each other;
both of the X direction and the Y direction are perpendicular to the Z direction;
a high-resistance area, a first low-resistance area, and a second low-resistance area are formed in the semiconductor film;
when viewed in a top view, the high-resistance area has a width WRH along the Y direction;
when viewed in a top view, the first low-resistance area has a width WRL 1 along the Y direction;
when viewed in a top view, the second low-resistance area has a width WRL 2 along the Y direction;
the value of the width WRH is not less than zero;
the value of the width WRL 1 is not less than zero;
the value of the width WRL 2 is not less than zero;
when viewed in a top view, the high-resistance area, the first low-resistance area, and the second low-resistance area are interposed between the first upper gate electrode and the second upper gate electrode;
when viewed in a top view, the first low-resistance area is interposed between the first upper gate electrode and the high-resistance area;
when viewed in a top view, the second low-resistance area is interposed between the second upper gate electrode and the high-resistance area; and
when viewed in a top view, the high-resistance area is interposed between the first low-resistance area and the second low-resistance area;
a step (b) of applying pulse voltages V 1 and V 2 to the first upper gate electrode and the second upper gate electrode, respectively, for a period T 1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V 3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRL 1 and WRL 2 and so as to decrease the value of the width WRH, wherein
the absolute value of the pulse voltage V 1 is smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film;
the absolute value of the pulse voltage V 2 is smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film; and
the voltage Vs, the voltage Vd, the voltage V 3 , the pulse voltage V 1 , and the pulse voltage V 2 satisfy the following relationship (I):
Vs,Vd,V 3 >V 1 ,V 2 (1); and
a step (c) of repeating the step (b) n times (n represents an integer of two or more), until a resistance value between the source electrode and the drain electrode becomes a predetermined value or less.
2. The method according to claim 1 , wherein
the ferroelectric film is in contact with the semiconductor film.
3. The method according to claim 1 , wherein
the following relationships (II) and (III) are satisfied:
Vs=Vd=V 3 (II)
V 1 =V 2 <V 3 (III).
4. The method according to claim 1 , wherein
n is three or more.
5. The method according to claim 1 , wherein
n is five or more.
6. The method according to claim 1 , wherein
n is ten or more.
7. The method according to claim 1 , wherein
before the step (b) is conducted, both of the values of widths WRL 1 and WRL 2 are zero.
8. The method according to claim 1 , wherein
after the step (c) is conducted, the value of the width WRH is zero.
9. A method for operating a nonvolatile semiconductor device, the method comprising steps of:
a step (a) of preparing the nonvolatile semiconductor device, wherein
the nonvolatile semiconductor device comprises a lower gate electrode film, a ferroelectric film, a semiconductor film, a source electrode, a drain electrode, a first upper gate electrode, and a second upper gate electrode;
the lower gate electrode film, the ferroelectric film, and the semiconductor film are stacked in this order;
the source electrode, the drain electrode, the first upper gate electrode, and the second upper gate electrode are formed on the semiconductor film;
Z direction represents a stack direction of the lower gate electrode film, the ferroelectric film, and the semiconductor film;
when viewed in a top view, the source electrode and the drain electrode face each other along X direction;
when viewed in a top view, the first upper gate electrode and the second upper gate electrode face each other along Y direction;
the X direction and the Y direction are perpendicular to each other;
both of the X direction and the Y direction are perpendicular to the Z direction;
a high-resistance area, a first low-resistance area, and a second low-resistance area are formed in the semiconductor film;
when viewed in a top view, the high-resistance area has a width WRH along the Y direction;
when viewed in a top view, the first low-resistance area has a width WRL 1 along the Y direction;
when viewed in a top view, the second low-resistance area has a width WRL 2 along the Y direction;
the value of the width WRH is not less than zero;
the value of the width WRL 1 is not less than zero;
the value of the width WRL 2 is not less than zero;
when viewed in a top view, the high-resistance area, the first low-resistance area, and the second low-resistance area are interposed between the first upper gate electrode and the second upper gate electrode;
when viewed in a top view, the first low-resistance area is interposed between the first upper gate electrode and the high-resistance area;
when viewed in a top view, the second low-resistance area is interposed between the second upper gate electrode and the high-resistance area; and
when viewed in a top view, the high-resistance area is interposed between the first low-resistance area and the second low-resistance area;
a step (b) of applying pulse voltages V 1 and V 2 to the first upper gate electrode and the second upper gate electrode, respectively, for a period T 1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V 3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRL 1 and WRL 2 and so as to decrease the value of the width WRH, wherein
the absolute value of the pulse voltage V 1 is smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film;
the absolute value of the pulse voltage V 2 is smaller than that of a voltage necessary to invert all the polarizations included in the ferroelectric film; and
the voltage Vs, the voltage Vd, the voltage V 3 , the pulse voltage V 1 , and the pulse voltage V 2 satisfy the following relationship (I):
Vs,Vd,V 3 >V 1 ,V 2 (I); and
a step (c) of applying the pulse voltages V 1 and V 2 again to the first upper gate electrode and the second upper gate electrode, respectively, for the period T 1 , while voltages Vs, Vd, and V 3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRL 1 and WRL 2 more and so as to decrease the value of the width WRH more.
10. The method according to claim 9 , wherein
the ferroelectric film is in contact with the semiconductor film.
11. The method according to claim 9 , wherein
the following relationships (II) and (III) are satisfied:
Vs=Vd=V 3 (II)
V 1 =V 2 <V 3 (III).
12. The method according to claim 9 , wherein
n is three or more.
13. The method according to claim 9 , wherein
n is five or more.
14. The method according to claim 9 , wherein
n is ten or more.
15. The method according to claim 9 , wherein
before the step (b) is conducted, both of the values of widths WRL 1 and WRL 2 are zero.
16. The method according to claim 9 , wherein
after the step (c) is conducted, the value of the width WRH is zero.