Power circuit and wireless network adapter
View Patent ↗The present invention provides a power circuit, including a current-limiting chip, a current-limiting value setting circuit, and a baseband chip. A current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit. The general-purpose input/output port is configured to generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value. In the other time sequence periods of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a second signal so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value. The first current-limiting value is greater than the second current-limiting value.
1. A power circuit, comprising:
a current-limiting value setting circuit;
a baseband chip;
a current-limiting chip, wherein a current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit, wherein the general-purpose input/output port is configured to:
generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value; and
generate a second signal in other time sequence periods of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value, wherein the first current-limiting value is greater than the second current-limiting value.
2. The power circuit according to claim 1 ,
wherein the current-limiting value setting circuit comprises a first impedor and a second impedor,
wherein the current setting port of the current-limiting chip is connected to the general-purpose input/output port of the baseband chip through the first impedor,
wherein the general-purpose input/output port of the baseband chip is connected to a ground potential node through the second impedor,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level, and
wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high-impedance state.
3. The power circuit according to claim 1 ,
wherein the current-limiting value setting circuit comprises a third impedor and a fourth impedor,
wherein the current setting port of the current-limiting chip is connected to the general-purpose input/output port of the baseband chip through the third impedor,
wherein the general-purpose input/output port of the baseband chip is connected to a ground potential node through the fourth impedor,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level, and
wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high-impedance state.
4. The power circuit according to claim 1 ,
wherein the current-limiting value setting circuit comprises a fifth impedor, a sixth impedor, and a MOS transistor,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the fifth impedor,
wherein a drain electrode of the MOS transistor is connected to the current setting port of the current-limiting chip, a gate electrode of the MOS transistor is connected to the general-purpose input/output port of the baseband chip, and a source electrode of the MOS transistor is connected to the ground potential node through the sixth impedor,
wherein the MOS transistor is an N-channel MOS transistor, wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a high level and the drain electrode of the MOS transistor is conducted with the source electrode, and wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a low level and the drain electrode of the MOS transistor is disconnected with the source electrode.
5. The power circuit according to claim 1 ,
wherein the current-limiting value setting circuit comprises a fifth impedor, a sixth impedor, and a MOS transistor,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the fifth impedor,
wherein a drain electrode of the MOS transistor is connected to the current setting port of the current-limiting chip, a gate electrode of the MOS transistor is connected to the general-purpose input/output port of the baseband chip, and a source electrode of the MOS transistor is connected to the ground potential node through the sixth impedor,
wherein the MOS transistor is a P-channel MOS transistor, wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level and the drain electrode of the MOS transistor is conducted with the source electrode, and wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high level and the drain electrode of the MOS transistor is disconnected with the source electrode.
6. The power circuit according to claim 1 ,
wherein the current-limiting value setting circuit comprises a seventh impedor, an eighth impedor, and an analog switch,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the seventh impedor,
wherein a first channel of the analog switch is connected to the current setting port of the current-limiting chip, a second channel of the analog switch is connected to the ground potential node through the eighth impedor, and a control port of the analog switch is connected to the general-purpose input/output port of the baseband chip,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a high level, and the first channel of the analog switch is conducted with the second channel, and
wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a low level, and the first channel of the analog switch is disconnected with the second channel.
7. The power circuit according to claim 1 , further comprising a capacitor, wherein one end of the capacitor is connected to a current output port of the current-limiting chip, and the other end of the capacitor is connected to a ground potential node.
8. The power circuit according to claim 1 , further comprising a power management unit, wherein a current input port of the power management unit is connected to a current output port of the current-limiting chip, and wherein a current output port of the power management unit is connected to a current input port of the baseband chip.
9. A wireless network adapter comprising a power circuit, the power circuit comprising
a current-limiting value setting circuit, and
a baseband chip;
a current-limiting chip, wherein a current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit, wherein the general-purpose input/output port is configured to:
generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value; and
generate a second signal in other time sequence periods of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value, and wherein the first current-limiting value is greater than the second current-limiting value.
10. The wireless network adapter according to claim 9 ,
wherein the current-limiting value setting circuit comprises a first impedor and a second impedor,
wherein the current setting port of the current-limiting chip is connected to the general-purpose input/output port of the baseband chip through the first impedor, and the general-purpose input/output port of the baseband chip is connected to a ground potential node through the second impedor,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level, and
wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high-impedance state.
11. The wireless network adapter according to claim 9 ,
wherein the current-limiting value setting circuit comprises a third impedor and a fourth impedor,
wherein the current setting port of the current-limiting chip is connected to the general-purpose input/output port of the baseband chip through the third impedor, and the general-purpose input/output port of the baseband chip is connected to a ground potential node through the fourth impedor,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level; and in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high-impedance state.
12. The wireless network adapter according to claim 9 ,
wherein the current-limiting value setting circuit comprises a fifth impedor, a sixth impedor, and a MOS transistor,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the fifth impedor,
wherein a drain electrode of the MOS transistor is connected to the current setting port of the current-limiting chip, a gate electrode of the MOS transistor is connected to the general-purpose input/output port of the baseband chip, and a source electrode of the MOS transistor is connected to the ground potential node through the sixth impedor,
wherein the MOS transistor is an N-channel MOS transistor, wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a high level and the drain electrode of the MOS transistor is conducted with the source electrode, and wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a low level and the drain electrode of the MOS transistor is disconnected with the source electrode.
13. The wireless network adapter according to claim 9 ,
wherein the current-limiting value setting circuit comprises a fifth impedor, a sixth impedor, and a MOS transistor,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the fifth impedor,
wherein a drain electrode of the MOS transistor is connected to the current setting port of the current-limiting chip, a gate electrode of the MOS transistor is connected to the general-purpose input/output port of the baseband chip, and a source electrode of the MOS transistor is connected to the ground potential node through the sixth impedor,
wherein the MOS transistor is a P-channel MOS transistor, wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a low level and the drain electrode of the MOS transistor is conducted with the source electrode, and wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a high level and the drain electrode of the MOS transistor is disconnected with the source electrode.
14. The wireless network adapter according to claim 9 ,
wherein the current-limiting value setting circuit comprises a seventh impedor, an eighth impedor, and an analog switch,
wherein the current setting port of the current-limiting chip is connected to a ground potential node through the seventh impedor,
wherein a first channel of the analog switch is connected to the current setting port of the current-limiting chip, a second channel of the analog switch is connected to the ground potential node through the eighth impedor, and a control port of the analog switch is connected to the general-purpose input/output port of the baseband chip,
wherein in the first time sequence period of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a high level, and the first channel of the analog switch is conducted with the second channel, and
wherein in the other time sequence periods of timeslot transmitting and a non-timeslot-transmitting period of the baseband chip, the general-purpose input/output port generates a low level, and the first channel of the analog switch is disconnected with the second channel.
15. The wireless network adapter according to claim 9 , wherein the power circuit further comprises a capacitor, wherein one end of the capacitor is connected to a current output port of the current-limiting chip, and the other end of the capacitor is connected to a ground potential node.
16. The wireless network adapter according to claim 9 , wherein the power circuit further comprises a power management unit, wherein a current input port of the power management unit is connected to a current output port of the current-limiting chip, and wherein a current output port of the power management unit is connected to a current input port of the baseband chip.
17. The wireless network adapter according to claim 9 , further comprising a general-purpose serial bus interface, wherein the general-purpose serial bus interface is connected to the current-limiting chip so that an external power supply supplies power to the wireless network adapter through the general-purpose serial bus interface.