IP Library Granted Patent US 9,495,204
Granted Patent B2
US 9,495,204 · App. 14/147,974 · Granted Nov 15, 2016

Constructing a logical tree topology in a parallel computer

Inventors: Charles J. Archer (Hillsboro, OR); Nysal Jan K. A. (Bangalore, IN); Sameh S. Sharkawi (Cypress, TX)
Assignee: International Business Machines Corporation
G06F9/4843G06F9/5061G06F9/5066
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Quick Facts
Patent No.
US 9,495,204
App. No.
14/147,974
Granted
Nov 15, 2016
Kind
B2
Abstract

Constructing a logical tree topology in a parallel computer that includes compute nodes, where each compute node includes a hardware acceleration unit and executes an identical number of tasks and the tasks of each node have a rank, includes: creating hardware acceleration groups, with each hardware acceleration group including one task from each node, where the one task from each node has the same rank; assigning one task of a root compute node as a global root of the logical tree topology; assigning tasks of the root compute node other than the global root as local children of the global root; and assigning each of the global root and local children of the root compute node as a root of a subtree of tasks, wherein each subtree comprises the tasks of a hardware acceleration group.

Claims (32)

1. An apparatus for constructing a logical tree topology in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a hardware acceleration unit and executing an identical number of tasks, wherein the tasks of each node have a rank, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

creating a plurality of hardware acceleration groups, each hardware acceleration group comprising one task from each compute node, the one task from each compute node having the same rank;

assigning one task of a root compute node as a global root of the logical tree topology;

assigning tasks of the root compute node other than the global root as local children of the global root;

assigning each of the global root and local children of the root compute node as a root of a subtree of tasks, wherein each subtree comprises the tasks of a hardware acceleration group;

performing a broadcast operation in the logical tree topology including:

transmitting broadcast data by the global root of the root compute node to the local children of the root compute node through shared memory; and

transmitting the broadcast data in parallel by the global root and local children to tasks of the global root and local children's subtrees.

2. The apparatus of claim 1 , wherein the number of tasks executing on each compute node is less than the number of compute nodes.

3. The apparatus of claim 1 , wherein the method is carried out upon establishment of an operational group of the tasks.

4. The apparatus of claim 1 , further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of performing a gather operation in the logical tree topology including:

transmitting, by each task of a compute node other than the root compute node, gather data to the root of the task's subtree; and

transmitting the gather data through shared memory by each of the subtree roots to the global root.

5. The apparatus of claim 1 , further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of performing a reduce operation in the logical tree topology including:

transmitting, by each task of a compute node other than the root compute node, reduce data to the root of the task's subtree including performing a reduction operation on the reduce data; and

transmitting the reduce data through shared memory by each of the subtree roots to the global root including performing the reduction operation on the reduce data.

6. A computer program product for constructing a logical tree topology in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a hardware acceleration unit and executing an identical number of tasks, wherein the tasks of each node have a rank, the computer program product disposed upon a computer readable storage medium, wherein the computer readable storage medium is not a signal, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

creating a plurality of hardware acceleration groups, each hardware acceleration group comprising one task from each compute node, the one task from each compute node having the same rank;

assigning one task of a root compute node as a global root of the logical tree topology;

assigning tasks of the root compute node other than the global root as local children of the global root;

assigning each of the global root and local children of the root compute node as a root of a subtree of tasks, wherein each subtree comprises the tasks of a hardware acceleration group;

performing a broadcast operation in the logical tree topology including:

transmitting broadcast data by the global root of the root compute node to the local children of the root compute node through shared memory; and

transmitting the broadcast data in parallel by the global root and local children to tasks of the global root and local children's subtrees.

7. The computer program product of claim 6 , wherein the number of tasks executing on each compute node is less than the number of compute nodes.

8. The computer program product of claim 6 , wherein the method is carried out upon establishment of an operational group of the tasks.

9. The computer program product of claim 6 , further comprising computer program instructions that, when executed, cause a computer to carry out the step of performing a gather operation in the logical tree topology including:

transmitting, by each task of a compute node other than the root compute node, gather data to the root of the task's subtree; and

transmitting the gather data through shared memory by each of the subtree roots to the global root.

10. The computer program product of claim 6 , further comprising computer program instructions that, when executed, cause a computer to carry out the step of performing a reduce operation in the logical tree topology including:

transmitting, by each task of a compute node other than the root compute node, reduce data to the root of the task's subtree including performing a reduction operation on the reduce data; and

transmitting the reduce data through shared memory by each of the subtree roots to the global root including performing the reduction operation on the reduce data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2014
From: ARCHER, CHARLES J.; K.A., NYSAL JAN; SHARKAWI, SAMEH S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031895/0816 →
Continuity (1)
Related Publication 20150193270A1 · Jul 9, 2015