IP Library Granted Patent US 9,152,164
Granted Patent B2
US 9,152,164 · App. 14/149,773 · Granted Oct 6, 2015

Constant current source circuit

Inventor: Akira Ide (Tokyo, JP)
Assignee: PS4 Luxco S.a.r.l.
G05F3/262
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Quick Facts
Patent No.
US 9,152,164
App. No.
14/149,773
Granted
Oct 6, 2015
Kind
B2
Abstract

A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

Claims (71)

1. A current source comprising:

a first MOS transistor of a first channel type including:

a drain connected to an output terminal; and

a source directly connected to a first power supply voltage;

a second MOS transistor of the first channel type including:

a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first MOS transistor; and

a source directly connected to the first power supply voltage;

a third MOS transistor of a second channel type opposite the first channel type including:

a drain connected to the drain of the second MOS transistor;

a fourth MOS transistor of the second channel type including:

a drain connected to the source of the third MOS transistor;

a gate connected to a first bias voltage; and

a source directly connected to a second power supply voltage; and

a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

2. The current source as claimed in claim 1 , wherein the drain of the first MOS transistor is connected to the output terminal through a fifth MOS transistor of the first channel type including:

a drain connected to the output terminal;

a gate connected to a second bias voltage; and

a source directly connected to the drain of the first MOS transistor.

3. The current source as claimed in claim 1 , further comprising:

a fifth MOS transistor of the second channel type, including:

a drain connected to the drain of the third MOS transistor;

a gate connected to a second bias voltage; and

a source connected to the source of the third MOS transistor.

4. The current source as claimed in claim 1 , wherein the control voltage generator comprises:

a fifth MOS transistor of the second channel type including:

a gate connected to the first bias voltage; and

a source directly connected to the second power supply voltage;

a sixth MOS transistor of the first channel type including:

a drain connected to the drain of the fifth MOS transistor;

a gate connected to the output terminal; and

a source connected to the gate of the third MOS transistor; and

a seventh MOS transistor of the first channel type including:

a drain connected to the gate of the third MOS transistor;

a gate connected to the gate of the first MOS transistor; and

a source directly connected to the first power supply voltage.

5. The current source as claimed in claim 4 , wherein the source of the sixth MOS transistor is connected to the gate of the third MOS transistor through a first resistor.

6. The current source as claimed in claim 5 , wherein the drain of the seventh MOS transistor is connected to the gate of the third MOS transistor through a second resistor.

7. The current source as claimed in claim 1 , further comprising:

a fifth MOS transistor of the first channel type including:

a drain connected to the drain of the first MOS transistor;

a gate connected to a second bias voltage; and

a source directly connected to the first power supply voltage.

8. A current source comprising:

a first MOS transistor of a first channel type including:

a drain connected to an output terminal; and

a source directly connected to a first power supply voltage;

a second MOS transistor of the first channel type including:

a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first MOS transistor; and

a source directly connected to the first power supply voltage;

a third MOS transistor of a second channel type opposite the first channel type including:

a drain connected to the drain of the second MOS transistor; and

a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor,

wherein the drain of the first MOS transistor is connected to the output terminal through a fourth MOS transistor of the first channel type including:

a drain connected to the output terminal;

a gate connected to a bias voltage; and

a source directly connected to the drain of the first MOS transistor.

9. A current source comprising:

a first MOS transistor of a first channel type including:

a drain connected to an output terminal; and

a source directly connected to a first power supply voltage;

a second MOS transistor of the first channel type including:

a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first MOS transistor; and

a source directly connected to the first power supply voltage;

a third MOS transistor of a second channel type opposite the first channel type including:

a drain connected to the drain of the second MOS transistor; and

a source directly connected to a second power supply voltage;

a fourth MOS transistor of the second channel type including:

a drain connected to the source of the third MOS transistor;

a gate connected to a first bias voltage; and

a source connected to the source of the third MOS transistor; and

a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046865/0667 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
Priority Claims (1)
JP 2007-258529 · Oct 2, 2007 · national
Continuity (2)
Continuation 12285089 · Sep 29, 2008
Related Publication 20140117969A1 · May 1, 2014