Incremental programming pulse optimization to reduce write errors
View Patent ↗In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed.
1. A data storage system comprising:
a processor;
memory connected to the processor, the memory comprising a plurality of multi-level memory cells;
a data storage element connected to the processor; and
computer executable program code configured to execute on the processor,
wherein the computer executable program code is configured to:
identify a first multi-level cell in the plurality of multi-level cells as being prone to write errors;
modify an incremental step programming pulse via applying more pulses to shift a mean voltage distribution associated with a least significant bit; and
apply the modified incremental step programming pulse to the first multi-level memory cell.
2. The system of claim 1 , wherein:
the computer executable program code is further configured to track a program/erase cycle count associated with the first multi-level memory cell; and
identifying that the first multi-level memory cell is prone to write errors comprises identifying that the program/erase cycle count has exceeded a count threshold.
3. The system of claim 1 , wherein:
the computer executable program code is further configured to anticipate at least one of a data retention duration and a number of read cycles associated with the first multi-level memory cell; and
identifying that the first multi-level memory cell is prone to write errors comprises identifying that the data retention duration has exceeded at least one of a duration threshold and a read frequency threshold.
4. The system of claim 1 , wherein modifying the incremental step programming pulse further comprises narrowing a pulse width to increase precision of programming.
5. The system of claim 1 , wherein modifying the incremental step programming pulse further comprises reducing a pulse amplitude to increase precision of programming.
6. The system of claim 1 , wherein modifying the incremental step programming pulse further comprises slowing a ramp-up of pulse magnitudes to increase precision of programming.
7. The system of claim 1 , wherein the computer executable program code is further configured to:
identify a second multi-level cell in the plurality of multi-level cells, such second multi-level cell not prone to write errors;
apply a standardized incremental step programming pulse to the first multi-level memory cell.
8. A method for programming multi-level memory cells comprising:
identifying a first multi-level cell as being prone to write errors;
modifying an incremental step programming pulse via applying more pulses to shift a mean voltage distribution associated with a least significant bit; and
applying the modified incremental step programming pulse to the first multi-level memory cell.
9. The method of claim 8 , further comprising tracking a program/erase cycle count associated with the first multi-level memory cell,
wherein identifying that the first multi-level memory cell is prone to write errors comprises identifying that the program/erase cycle count has exceeded a count threshold.
10. The method of claim 8 , further comprising anticipating at least one of a data retention duration and a number of read cycles associated with the first multi-level memory cell,
wherein identifying that the first multi-level memory cell is prone to write errors comprises identifying that at least one of the data retention duration and the number of read cycles has exceeded a threshold.
11. The method of claim 8 , wherein modifying the incremental step programming further pulse comprises narrowing a pulse width to increase precision of programming.
12. The method of claim 8 , wherein modifying the incremental step programming pulse further comprises reducing a pulse amplitude to increase precision of programming.
13. The method of claim 8 , wherein modifying the incremental step programming pulse further comprises slowing a ramp-up of pulse magnitudes to increase precision of programming.
14. A low-density parity-check decoder comprising:
a processor;
memory connected to the processor, the memory comprising a plurality of multi-level memory cells; and
computer executable program code,
wherein the computer executable program code is configured to:
track a program/erase cycle count;
anticipate at least one of a data retention duration and a number of read cycles associated with the first multi-level memory cell;
identify a first multi-level cell in the plurality of multi-level cells as being prone to write errors based on the program/erase cycle count, the data retention duration and a read frequency exceeding a threshold;
modify an incremental step programming pulse via applying more pulses to shift a mean voltage distribution associated with a least significant bit; and
apply the modified incremental step programming pulse to the first multi-level memory cell.
15. The low-density parity-check decoder of claim 14 , wherein modifying the incremental step programming pulse further comprises narrowing a pulse width to increase precision of programming.
16. The low-density parity-check decoder of claim 14 , wherein modifying the incremental step programming pulse further comprises reducing a pulse amplitude to increase precision of programming.
17. The low-density parity-check decoder of claim 14 , wherein modifying the incremental step programming pulse further comprises slowing a ramp-up of pulse magnitudes to increase precision of programming.