Detection/erasure of random write errors using converged hard decisions
View Patent ↗A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing.
1. A computer apparatus comprising:
a processor;
a memory connected to the processor; and
computer executable program code embodied in the memory and configured to execute on the processor,
wherein the computer executable program code configures the processor to:
detect voltages in a multi-level memory cell wherein the multi-level memory cell is configured to store at least two bits of a low-density parity-check codeword;
determine that a first bit of the at least two bits correctly decoded;
receive bit page data corresponding to the first bit; and
erase a log-likelihood ratio associated with a second bit in the at least two bits.
2. The computer apparatus of claim 1 , wherein the computer executable program code further configures the processor to:
perform a sweep of voltages associated with the multi-level memory cell; and
determine one or more threshold voltages associated with a boundary between cell states of a most significant bit based on the sweep.
3. The computer apparatus of claim 2 , wherein the computer executable program code further configures the processor to:
perform a sweep of voltages associated with the multi-level memory cell; and
determine one or more threshold voltages associated with a boundary between cell states of a least significant bit based on the sweep.
4. The computer apparatus of claim 3 , wherein the computer executable program code further configures the processor to perform two voltage reads, each corresponding to potential states of the second bit, and each corresponding to a reliable zone.
5. The computer apparatus of claim 3 , wherein the second bit is a most significant bit in the multi-level memory cell.
6. The computer apparatus of claim 3 , wherein the second bit is a least significant bit in the multi-level memory cell.
7. The computer apparatus of claim 1 , wherein the computer executable program code further configures the processor to iteratively decode a low-density parity-check codeword at least partially stored in the multi-level memory cell.
8. A method for correcting errors in a low-density parity-check code comprising:
detecting voltages in a multi-level memory cell wherein the multi-level memory cell is configured to store at least two bits of a low-density parity-check codeword;
determining that a first bit of the at least two bits correctly decoded;
receiving bit page data corresponding to the first bit; and
erasing a log-likelihood ratio associated with a second bit in the at least two bits.
9. The method of claim 8 , further comprising:
performing a sweep of voltages associated with the multi-level memory cell; and
determining one or more threshold voltages associated with a boundary between cell states of a most significant bit based on the sweep.
10. The method of claim 9 , further comprising:
performing a sweep of voltages associated with the multi-level memory cell; and
determining one or more threshold voltages associated with a boundary between cell states of a least significant bit based on the sweep.
11. The method of claim 10 , further comprising performing two voltage reads, each corresponding to potential states of the second bit, and each corresponding to a reliable zone.
12. The method of claim 10 , wherein the second bit is a most significant bit in the multi-level memory cell.
13. The method of claim 10 , wherein the second bit is a least significant bit in the multi-level memory cell.
14. The method of claim 8 , further comprising iteratively decoding a low-density parity-check codeword at least partially stored in the multi-level memory cell.
15. A data storage system comprising:
a processor;
a memory connected to the processor;
a data storage element including a plurality of multi-level memory cells; and
computer executable program code embodied in the memory and configured to execute on the processor,
wherein:
each of the plurality of multi-level memory cells is configured to store a most significant bit and a least significant bit represented as four potential voltage values, each corresponding to a cell state;
each of the plurality of multi-level memory cells is configured to store bits of a low-density parity-check codeword; and
the computer executable program code configures the processor to:
detect voltages in a multi-level memory cell in the data storage element;
determine that a first bit of the multi-level memory cell correctly decoded;
receive bit page data corresponding to the first bit; and
erase a log-likelihood ratio associated with a second bit of the multi-level memory cell.
16. The data storage system of claim 15 , wherein the computer executable program code further configures the processor to:
perform a sweep of voltages associated with the multi-level memory cell; and
determine one or more threshold voltages associated with a boundary between cell states of the most significant bit based on the sweep.
17. The data storage system of claim 16 , wherein the computer executable program code further configures the processor to:
perform a sweep of voltages associated with the multi-level memory cell; and
determine one or more threshold voltages associated with a boundary between cell states of the least significant bit based on the sweep.
18. The data storage system of claim 17 , wherein the computer executable program code further configures the processor to perform two voltage reads, each corresponding to potential states of the second bit, and each corresponding to a reliable zone.
19. The data storage system of claim 17 , wherein the second bit is the most significant bit in the multi-level memory cell.
20. The data storage system of claim 17 , wherein the second bit is the least significant bit in the multi-level memory cell.