Patent Application

App. No. 14/151,576

Abstract

Claims (37)

1 . A semiconductor device comprising:

a silicon layer;

a tapered insulating layer formed on the silicon layer; and

a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer,

wherein the taper of the tapered insulating layer is in the lower surface of the tapered insulating layer,

and wherein the tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer.

2 . The device of claim 1 , wherein the semiconductor device is a high voltage semiconductor device.

3 . The device of claim 1 , wherein the tapered insulating layer extends downwardly into the silicon layer so that, in a first area, the silicon layer is thicker than the tapered insulating layer and so that, in a second area, the tapered insulating layer is thicker than the silicon layer.

4 . The device of claim 1 , further comprising:

a substrate; and

an insulation layer ( 102 ) formed above the substrate,

wherein the silicon layer ( 104 ) is formed on the insulation layer.

5 . The device of claim 1 , wherein the thickness of the silicon layer is 3 μm or less, and wherein the thickness of the tapered insulating layer is in the range of 5 nm-3000 nm.

6 . The device of claim 1 , wherein the at least 50% of the thickness of the tapered insulating layer is recessed in the silicon layer portion.

7 . The device of claim 1 , wherein the device comprises at least first and second terminals, and wherein a silicon layer portion and a tapered insulating layer portion extend laterally between the first and second terminals.

8 . The device of claim 7 , wherein the silicon layer is gradually doped so as to have a doping profile that varies laterally between the first and second terminals.

9 . The device of claim 7 , wherein the device comprises a transistor, and wherein the first terminal comprises a source of the transistor and the second terminals comprises a drain of the transistor.

10 . The device of claim 7 , further comprising:

a dielectric layer formed on the tapered insulating layer; and

a metal fieldplate formed on the dielectric layer,

wherein an electrical contact for at least one of the first and second terminals is formed in the metal layer.

11 . An electronic circuit comprising a semiconductor device according to claim 1 .

12 . A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a tapered insulating layer on a silicon layer; and

forming a plurality of Bipolar CMOS DMOS device layers above the tapered insulating layer,

and wherein the insulating layer is formed such that its taper is in its lower surface, the upper surface is substantially planar, and the tapered insulating layer is at least partially recessed in the silicon layer portion.

13 . The method of claim 12 , wherein forming a tapered insulating layer comprises:

providing a substrate layer;

forming an insulation layer on the substrate layer;

forming a Silicon-On-Insulation, SOI, layer on the insulation layer; and

forming a recessed oxide layer on the SOI layer.

14 . The method of claim 13 , wherein the step of forming a recessed oxide layer comprises:

forming an oxide layer on the SOI layer; covering one or more areas of the oxide layer with a masking layer to leave one or more exposed areas of the oxide layer;

using thermal oxidation to grow the one or more exposed areas of the oxide layer; and

planarising the upper surface of the oxide layer.

15 . The method of claim 13 , wherein the step of forming a recessed oxide layer further comprises, prior to forming an oxide layer the SOI layer, undertaking the step of:

selectively growing an oxide layer on the SOI layer and then removing the oxide layer to form a recess in the SOI layer.

Assignments (10)