Pre-fabricated substrate for printed electronic devices
View Patent ↗A pre-patterned substrate has a supporting material, a plurality of segments on the supporting material, a plurality of interdigitated line structures within each segment to allow formation of features, and an isolation region between the segments.
1. A pre-patterned substrate, comprising:
a supporting material;
a plurality of segments in direct contact with a surface of the supporting material;
a plurality of interdigitated parallel, coplanar lines within each segment to allow reconfigurable formation of features, each of the interdigitated lines electrically isolated from the other lines; and
an isolation region between the segments.
2. The substrate of claim 1 , wherein the substrate further comprises a buffer layer.
3. The substrate of claim 1 , wherein the supporting material comprises one of plastic, glass, silicon, and steel foil.
4. The substrate of claim 1 , wherein the interdigitated lines comprise one of silver, gold, platinum, and aluminum.
5. The substrate of claim 1 , wherein the interdigitated lines have a line width in the range of 1 nanometer to 10 micrometers.
6. The substrate of claim 1 , wherein the interdigitated lines have a channel length in the range of 1 nanometer to 100 micrometers.
7. The substrate of claim 1 , wherein spacing between interdigitated lines within one segment differs from spacing between parallel lines within at least one other segment.
8. The substrate of claim 1 , wherein interdigitated lines within one segment may have different channel lengths.
9. The substrate of claim 1 , further comprising a floating line in between two lines in a source and drain pair of lines.
10. The substrate of claim 1 , wherein the interdigitated lines comprise conductive lines on the substrate.
11. The substrate of claim 1 , wherein the interdigitated line structures comprise recessed channels in the substrate.
12. The substrate of claim 1 , wherein the interdigitated line structures comprise self-assembled organic molecules.
13. A method, comprising:
providing a substrate;
forming interdigitated coplanar, parallel lines in segments in contact with a surface of the substrate, each of the interdigitated lines electrically isolated from the other lines, to allow formation of reconfigurable features; and
defining isolation regions between the segments in which no interdigitated lines exist.
14. The method of claim 13 , wherein forming the interdigitated lines comprises forming conductive traces on a surface of the substrate.
15. The method of claim 13 , wherein forming the interdigitated line structures comprises forming recessed channels in the substrate.
16. The method of claim 13 , wherein forming the interdigitated line structures comprises depositing molecules of organic molecules, the organic molecules forming self-assembled monolayers.
17. The method of claim 13 , further comprising depositing a buffer layer on the substrate prior to forming the interdigitated lines.
18. The method of claim 13 , wherein forming the interdigitated lines comprises forming conductive interdigitated lines, the method further comprising:
depositing semiconductor ink over selected ones of the interdigitated lines;
conductively connecting a first set of the selected ones of the interdigitated lines that extend beyond the other of the interdigitated lines on one side of the ink together to form a source contact;
conductively connecting a second set of the selected ones of the interdigitated lines that extend beyond the other of the interdigitated lines on another side of the ink together to form a drain contact; and
forming a gate contact overlapping the source and drain contacts.