Memory architecture with local and global control circuitry
View Patent ↗A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.
1. A system comprising:
a memory block including a local control circuit that is operable to control a memory operation of the memory block, the local control circuit comprising:
a local sense amplifier, and
a local controller adapted to control timing for a memory access to the memory block; and
a global memory control circuit separate from the memory block and operable to communicate with the local control circuit, the global memory control circuit comprising:
a global sense amplifier operable to receive a sensed data state from the local sense amplifier.
2. The system of claim 1 , where the local sense amplifier is adapted to automatically shut off after indicating a sensed data state.
3. The system of claim 1 , where the local sense amplifier comprises a self-latching sense amplifier.
4. The system of claim 1 , where the local sense amplifier is adapted to receive an activation signal generated by a dummy column timing circuit.
5. The system of claim 1 , where:
the local control circuit further comprises a local wordline decoder; and
the global memory control circuit further comprises a global wordline decoder coupled to the local wordline decoder through a particular global wordline, and where the global wordline decoder is operable to:
activate the particular global wordline during a memory access to the memory block.
6. The system of claim 5 , where the local wordline decoder is operable to activate a local wordline when the particular global wordline is activated.
7. The system of claim 6 , where the local wordline decoder is operable to deactivate the local wordline when a bitline replica signal falls below a predetermined threshold.
8. A system comprising:
a first memory block including a first local control circuit that is operable to control a memory operation of the first memory block, the first local control circuit comprising:
a first local controller adapted to control timing for a memory access to the first memory block, and
a first local sense amplifier; and
a second memory block including a second local control circuit that is operable to control a memory operation of the second memory block, the second local control circuit comprising:
a second local controller adapted to control timing for a memory access to the second memory block, and
a second local sense amplifier; and
a global memory control circuit separate from the first and second memory blocks and operable to communicate with the first and second local control circuits, the global memory control circuit comprising:
a global sense amplifier operable to receive a sensed data state from the first local sense amplifier, the second local sense amplifier, or both.
9. The system of claim 8 , where the first local sense amplifier, the second local sense amplifier, or both, are adapted to automatically shut off after indicating a sensed data state.
10. The system of claim 8 , where the first local sense amplifier, the second local sense amplifier, or both, comprise a self-latching sense amplifier.
11. The system of claim 8 , where the first local sense amplifier, the second local sense amplifier, or both, are adapted to receive an activation signal generated by a dummy column timing circuit.
12. The system of claim 8 , where:
the first local control circuit further comprises a first local wordline decoder;
the second local control circuit further comprises a second local wordline decoder; and
the global memory control circuit further comprises a global wordline decoder coupled to the first local wordline decoder through a first global wordline and to the second local wordline decoder through a second global wordline, the global wordline decoder operable to activate the global wordline decoder is operable to:
activate the first global wordline during a memory access to the first memory block; and
activate the second global wordline during a memory access to the second memory block.
13. The system of claim 12 , where:
the first local wordline decoder is operable to activate a first local wordline in the first memory block when the first global wordline is activated; and
the second local wordline decoder is operable to activate a second local wordline in the second memory block when the second global wordline is activated.
14. The system of claim 13 , where the first local wordline decoder is operable to deactivate the first local wordline when a bitline replica signal falls below a predetermined threshold.
15. A method comprising:
from a local sense amplifier for a memory block:
sending a sensed data state of one or more bitlines of the memory block to a global sense amplifier external to the memory block; and
at a local controller for the memory block, controlling timing for a memory access to the memory block.
16. The method of claim 15 , further comprising:
automatically shutting off the local sense amplifier after sending the sensed data state.
17. The method of claim 15 , further comprising:
generating an activation signal for the local sense amplifier with a dummy column timing circuit; and
providing the activation signal to the local sense amplifier.
18. The method of claim 15 , further comprising:
self-latching the sensed data state by the local sense amplifier for sending the sensed data state to the global sense amplifier.