Bus controller, bus control system and network interface

1. A bus controller for use in a bus control system for a semiconductor circuit in which data is transmitted between first and second nodes over a network of buses, the controller being connected directly to the first node and comprising:

a route load detector which detects loads on respective routes that form at least one of a forward route group and a backward route group, the forward route group being comprised of two or more routes leading from the first node to the second node, the backward route group being comprised of two or more routes leading from the second node to the first node;

a candidate route extraction circuit which extracts a candidate route from the at least one group of routes so that loads on the respective routes that form the group become as uniform as possible;

a selection rule storage which stores a predetermined selection rule, the selection rule comprising at least one of a selection rule that imposes no limitations on routes, a selection rule that designates a particular route to use, and a selection rule indicating that this is a non-rate-ensured flow;

a route determining circuit which determines the route to transmit the data based on the candidate route that has been extracted by the candidate route extraction circuit and the selection rule stored in the selection rule storage;

a header building circuit which generates header information that includes route information indicating the route that has been determined; and

a data communication circuit which transmits the data between the first and second nodes through the route that has been designated by reference to the header information.

2. The bus controller of claim 1 , wherein the route load detector detects, as the route load, a bus' operating bandwidth which is allocated to at least one of the forward and backward route groups.

3. The bus controller of claim 1 , wherein the at least one route group is the forward route group, and

the candidate route extraction circuit extracts, as the candidate route, one of the forward routes that has a lighter route load than any other route in the forward route group.

4. The bus controller of claim 1 , wherein the at least one route group is the backward route group, and

the candidate route extraction circuit extracts, as the candidate route, one of the backward routes that has a lighter route load than any other route in the backward route group.

5. The bus controller of claim 1 , wherein if the selection rule storage stores a selection rule indicating, when there are multiple flows as data transmission units, in what order those flows are to be used,

if another flow route which observes a predetermined order with respect to a new flow has already been determined and

if the selection rule indicating the predetermined order of flows is applied to the new flow,

the candidate route extraction circuit extracts the same route as that another flow route as the candidate route.

6. The bus controller of claim 1 , wherein if the selection rule storage stores a selection rule indicating that this is a non-rate-ensured flow,

if a non-rate-ensured flow route has already been determined and

if the selection rule indicating that this is a non-rate-ensured flow is applied to the new flow,

the candidate route extraction circuit extracts, as the candidate route, a different route from an existent non-rate-ensured flow route.

7. The bus controller of claim 1 , wherein if the selection rule storage stores a selection rule that designates a particular route to use, and

if the selection rule that designates the particular route to use is applied to the new flow,

the route determining circuit determines the route designated by the selection rule to be the route to transmit the data, no matter what route has been extracted by the route extraction circuit.

8. The bus controller of claim 1 , wherein if a non-rate-ensured flow route has already been determined,

if the selection rule storage stores a selection rule indicating that this is a non-rate-ensured flow, and

if the selection rule indicating that this is the non-rate-ensured flow is applied to the new flow,

the candidate route extraction circuit extracts, as the candidate route, a different route from an existent non-rate-ensured flow route.

9. The bus controller of claim 1 , wherein the selection rule storage further stores degree of priority information indicating the degrees of priorities of flows at the first node, and

the candidate route extraction circuit extracts, as the candidate route, a route to which a flow with a low degree of priority has been allocated by reference to the degree of priority information.

10. The bus controller of claim 1 , wherein the data communication circuit transmits and receives the data on a packet basis, and

the header building circuit stores the header information in the header of each packet.

11. The bus controller of claim 1 , wherein the selection rule is applied to flows having the same degree of priority.

12. A bus control system comprising:

at least one first node;

at least one second node;

the bus controller of claim 1 which is directly connected to the at least one first node; and

a network of buses which form a plurality of routes between the bus controller and the at least one second node,

wherein the bus control system transmits data between the at least one first node and the at least one second node over the buses.

13. The bus control system of claim 12 , further comprising a migrator which exchanges data flows that are allocated to the respective memories,

wherein the memories form the at least one second node,

a plurality of routes are provided between the at least one first node and the memories, and

the migrator exchanges the data flows allocated to the respective memories based on operating bandwidths of the buses that are allocated to the routes and on storage spaces that are used on the respective memories.

14. The bus control system of claim 12 , wherein the routes are arranged as a plurality of buses that are spatially separated from each other.

15. The bus control system of claim 12 , wherein the routes are arranged to form a single signal line on the buses.

16. The bus control system of claim 15 , wherein the routes are formed by subjecting the single signal line on the buses to time division multiplexing.

17. The bus control system of claim 12 , wherein the network of buses includes local buses with the multiple routes and a system bus, and

the system further includes a bus bridge which connects the local buses and the system bus together.

18. A network interface for use in the bus control system of claim 12 , the interface comprising:

a bandwidth information management circuit which manages bandwidth information that is information about the bandwidth of a flow which is currently allocated as a data transmission unit to an associated route; and

a data communication circuit which transmits and receives data from the first node to the second node and vice versa.

19. The network interface of claim 18 , wherein the bandwidth information management circuit outputs the bandwidth information via the data communication circuit in response to a request from the route load detector of the bus controller which is included in the bus control system.

20. The network interface of claim 18 , further comprising a backward route header building circuit which generates information designating the backward route by reference to route information that is included in the header information to indicate the backward route and which stores, along with information specifying an address, the backward route designating information in the header of a packet.