Dynamic random access memory for communications systems

1. A system comprising:

an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells, wherein:

said first one or more DRAM cells is refreshed by said memory refresh circuit;

said first one or more DRAM cells is used, by said digital logic circuit, for storage of data which is overwritten, by new data, at less than a threshold frequency;

said second one or more DRAM cells is not refreshed by any memory refresh circuit; and

said second one or more DRAM cells is used, by said digital logic circuit, for storage of data which is overwritten, by new data, at greater than said threshold frequency.

2. The system of claim 1 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

3. The system of claim 1 , wherein:

said first one or more DRAM cells is used, by said digital logic circuit, for storage of one or both of: a configuration parameter, and an instruction; and

said second one or more DRAM cells is used, by said digital logic circuit, for buffering of received and/or to-be-transmitted data.

4. The system of claim 1 , wherein:

said first one or more DRAM cells is used, by said digital logic circuit, for storage of a first type of data for which tolerance of errors is low relative to a second type of data; and

said second one or more DRAM cells is used, by said digital logic circuit, for storage of said second type of data.

5. The system of claim 1 , wherein:

said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word;

said first one or more DRAM cells holds first bits of data written to said memory word by said digital logic circuit;

said second one or more DRAM cells holds second bits of data written to said memory word by said digital logic circuit; and

said first bits of data are more significant than said second bits of data.

6. The system of claim 1 , wherein a rate at which said memory refresh circuit refreshes said first one or more DRAM cells is adjusted, by said digital logic circuit, during run-time of said integrated circuit.

7. The system of claim 6 , wherein said adjustment of said rate of refresh comprises an enable of refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and a disable of refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

8. The system of claim 6 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

9. The system of claim 6 , wherein said adjustment of said rate of refresh comprises variation of said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

10. A method comprising:

performing in an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells:

writing, by said digital logic circuit, data to, and reading data from, each of said first one or more DRAM cells and said second one or more DRAM cells;

refreshing, via said memory refresh circuit, said first one or more DRAM cells circuit, wherein said second one or more DRAM cells are not refreshed by any memory refresh circuit;

storing, by said digital logic circuit, data which is overwritten at less than a threshold frequency to said first one or more DRAM cells;

storing, by said digital logic circuit, data which is overwritten at greater than said threshold frequency to said second one or more DRAM cells.

11. The method of claim 10 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

12. The method of claim 10 , comprising:

storing, by said digital logic circuit, one or both of: a configuration parameter, and an instruction to said first one or more DRAM cells; and

buffering, by said digital logic circuit, received and/or to-be-transmitted data to said second one or more DRAM cells.

13. The system of claim 10 , comprising:

storing, by said digital logic circuit, a first type of data, for which tolerance of errors is low relative to a second type of data, to said first one or more DRAM cells; and

storing, by said digital logic circuit, said second type of data to said second one or more DRAM cells.

14. The method of claim 10 , wherein said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word, and comprising:

storing, by said digital logic circuit, first bits of data written to said memory word in said first one or more DRAM cells;

storing, by said digital logic circuit, second bits of data written to said memory word in said second one or more DRAM cells, wherein

said first bits of data are more significant than said second bits of data.

15. The system of claim 10 , comprising adjusting, by said digital logic circuit during run time of said integrated circuit, a rate at which said memory refresh circuit refreshes said first one or more DRAM cells.

16. The system of claim 15 , wherein said adjustment of said rate of refresh comprises enabling refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and disabling refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

17. The system of claim 15 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

18. The system of claim 15 , wherein said adjustment of said rate of refresh comprises varying said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

19. A system comprising:

an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells, wherein:

said first one or more DRAM cells is refreshed by said memory refresh circuit;

said first one or more DRAM cells is used, by said digital logic circuit, for storage of a first type of data for which tolerance of errors is low relative to a second type of data;

said second one or more DRAM cells is not refreshed by any memory refresh circuit; and

said second one or more DRAM cells is used, by said digital logic circuit, for storage of said second type of data.

20. The system of claim 19 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

21. The system of claim 19 , wherein:

said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word;

said first one or more DRAM cells holds first bits of data written to said memory word by said digital logic circuit;

said second one or more DRAM cells holds second bits of data written to said memory word by said digital logic circuit; and

said first bits of data are more significant than said second bits of data.

22. The system of claim 19 , wherein a rate at which said memory refresh circuit refreshes said first one or more DRAM cells is adjusted, by said digital logic circuit, during run-time of said integrated circuit.

23. The system of claim 22 , wherein said adjustment of said rate of refresh comprises an enable of refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and a disable of refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

24. The system of claim 22 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

25. The system of claim 22 , wherein said adjustment of said rate of refresh comprises variation of said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

26. A system comprising:

an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells, wherein:

said first one or more DRAM cells is refreshed by said memory refresh circuit;

said second one or more DRAM cells is not refreshed by any memory refresh circuit;

said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word;

said first one or more DRAM cells holds first bits of data written to said memory word by said digital logic circuit;

said second one or more DRAM cells holds second bits of data written to said memory word by said digital logic circuit; and

said first bits of data are more significant than said second bits of data.

27. The system of claim 26 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

28. The system of claim 26 , wherein:

said first one or more DRAM cells is used, by said digital logic circuit, for storage of one or both of: a configuration parameter, and an instruction; and

said second one or more DRAM cells is used, by said digital logic circuit, for buffering of received and/or to-be-transmitted data.

29. The system of claim 26 , wherein a rate at which said memory refresh circuit refreshes said first one or more DRAM cells is adjusted, by said digital logic circuit, during run-time of said integrated circuit.

30. The system of claim 29 , wherein said adjustment of said rate of refresh comprises an enable of refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and a disable of refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

31. The system of claim 29 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

32. The system of claim 29 , wherein said adjustment of said rate of refresh comprises variation of said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

33. A system comprising:

an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells, wherein:

said first one or more DRAM cells is refreshed by said memory refresh circuit;

said second one or more DRAM cells is not refreshed by any memory refresh circuit;

a rate at which said memory refresh circuit refreshes said first one or more DRAM cells is adjusted, by said digital logic circuit, during run-time of said integrated circuit; and

said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

34. The system of claim 33 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

35. The system of claim 33 , wherein:

said first one or more DRAM cells is used, by said digital logic circuit, for storage of one or both of: a configuration parameter, and an instruction; and

said second one or more DRAM cells is used, by said digital logic circuit, for buffering of received and/or to-be-transmitted data.

36. A system comprising:

an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells, wherein:

said first one or more DRAM cells is refreshed by said memory refresh circuit;

said second one or more DRAM cells is not refreshed by any memory refresh circuit;

a rate at which said memory refresh circuit refreshes said first one or more DRAM cells is adjusted, by said digital logic circuit, during run-time; and

said adjustment of said rate of refresh comprises variation of said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

37. The system of claim 36 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

38. The system of claim 36 , wherein:

said first one or more DRAM cells is used, by said digital logic circuit, for storage of one or both of: a configuration parameter, and an instruction; and

said second one or more DRAM cells is used, by said digital logic circuit, for buffering of received and/or to-be-transmitted data.

39. A method comprising:

performing in an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells:

writing, by said digital logic circuit, data to, and reading data from, each of said first one or more DRAM cells and said second one or more DRAM cells;

refreshing, via said memory refresh circuit, said first one or more DRAM cells circuit, wherein said second one or more DRAM cells are not refreshed by any memory refresh circuit;

storing, by said digital logic circuit, a first type of data, for which tolerance of errors is low relative to a second type of data, to said first one or more DRAM cells; and

storing, by said digital logic circuit, said second type of data to said second one or more DRAM cells.

40. The method of claim 39 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

41. The method of claim 39 , wherein said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word, and comprising:

storing, by said digital logic circuit, first bits of data written to said memory word in said first one or more DRAM cells;

storing, by said digital logic circuit, second bits of data written to said memory word in said second one or more DRAM cells, wherein said first bits of data are more significant than said second bits of data.

42. The system of claim 39 , comprising adjusting, by said digital logic circuit during run time of said integrated circuit, a rate at which said memory refresh circuit refreshes said first one or more DRAM cells.

43. The system of claim 42 , wherein said adjustment of said rate of refresh comprises enabling refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and disabling refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

44. The system of claim 42 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

45. The system of claim 42 , wherein said adjustment of said rate of refresh comprises varying said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

46. A method comprising:

performing in an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells:

writing, by said digital logic circuit, data to, and reading data from, each of said first one or more DRAM cells and said second one or more DRAM cells, wherein said first one or more DRAM cells and said second one or more DRAM cells are part of a single memory word;

refreshing, via said memory refresh circuit, said first one or more DRAM cells circuit, wherein said second one or more DRAM cells are not refreshed by any memory refresh circuit;

storing, by said digital logic circuit, first bits of data written to said memory word in said first one or more DRAM cells;

storing, by said digital logic circuit, second bits of data written to said memory word in said second one or more DRAM cells, wherein said first bits of data are more significant than said second bits of data.

47. The method of claim 46 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

48. The method of claim 46 , comprising:

storing, by said digital logic circuit, one or both of: a configuration parameter, and an instruction to said first one or more DRAM cells; and

buffering, by said digital logic circuit, received and/or to-be-transmitted data to said second one or more DRAM cells.

49. The system of claim 46 , comprising adjusting, by said digital logic circuit during run time of said integrated circuit, a rate at which said memory refresh circuit refreshes said first one or more DRAM cells.

50. The system of claim 49 , wherein said adjustment of said rate of refresh comprises enabling refresh of said first one or more DRAM cells by said memory refresh circuit during a first time interval and disabling refresh of said first one or more DRAM cells by said memory refresh circuit during a second time interval.

51. The system of claim 49 , wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

52. The system of claim 49 , wherein said adjustment of said rate of refresh comprises varying said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

53. A method comprising:

performing in an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells:

writing, by said digital logic circuit, data to, and reading data from, each of said first one or more DRAM cells and said second one or more DRAM cells;

refreshing, via said memory refresh circuit, said first one or more DRAM cells circuit, wherein said second one or more DRAM cells are not refreshed by any memory refresh circuit; and

adjusting, by said digital logic circuit during run time of said integrated circuit, a rate at which said memory refresh circuit refreshes said first one or more DRAM cells, wherein said adjustment of said rate of refresh is based on a forward error correction code rate of data stored in said first one or more DRAM cells.

54. The method of claim 53 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

55. The method of claim 53 , comprising:

storing, by said digital logic circuit, one or both of: a configuration parameter, and an instruction to said first one or more DRAM cells; and

buffering, by said digital logic circuit, received and/or to-be-transmitted data to said second one or more DRAM cells.

56. A method comprising:

performing in an integrated circuit comprising a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells:

writing, by said digital logic circuit, data to, and reading data from, each of said first one or more DRAM cells and said second one or more DRAM cells;

refreshing, via said memory refresh circuit, said first one or more DRAM cells circuit, wherein said second one or more DRAM cells are not refreshed by any memory refresh circuit; and

adjusting, by said digital logic circuit during run time of said integrated circuit, a rate at which said memory refresh circuit refreshes said first one or more DRAM cells, wherein said adjustment of said rate of refresh comprises varying said rate of refresh in response to variations of a symbol rate of signals to be buffered in said first one or more DRAM cells.

57. The method of claim 56 , wherein each of said first one or more DRAM cells and said second one or more DRAM cells is a one-transistor (“1T”) cell.

58. The method of claim 56 , comprising:

storing, by said digital logic circuit, one or both of: a configuration parameter, and an instruction to said first one or more DRAM cells; and

buffering, by said digital logic circuit, received and/or to-be-transmitted data to said second one or more DRAM cells.