IP Library Granted Patent US 9,241,169
Granted Patent B2
US 9,241,169 · App. 14/157,471 · Granted Jan 19, 2016

Raster to block conversion in a compressed domain

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Quick Facts
Patent No.
US 9,241,169
App. No.
14/157,471
Granted
Jan 19, 2016
Kind
B2
Abstract

A system for raster to block conversion in a compressed domain may include a raster to block encoder, a raster to block decoder, and a memory partitioned into a number of memory stripes having widths of a number of bits. The raster to block encoder may be configured to receive image information associated with pixels of an image in raster order, compress the image information associated with the pixels of the image to generate compressed bits that correspond to at least one of memory stripes, and write the compressed bits to the at least one of the memory stripes. The raster to block decoder may be configured to read, from at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block, and decode the number of the compressed bits to generate the at least one block.

Claims (53)

1. A method for raster to block conversion in a compressed domain, the method comprising:

determining a number of memory stripes of a memory that correspond to an image based at least on a size of the image, the memory stripes having memory stripe widths of a number of bits;

receiving image information associated with pixels of the image in raster order;

compressing the image information associated with the pixels of the image in the raster order to generate compressed bits;

writing the compressed bits to at least one of the memory stripes that corresponds to the pixels from which the compressed bits were generated;

reading, from the at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block; and

decoding the number of the compressed bits to generate the at least one block.

2. The method of claim 1 , further comprising:

providing the at least one block to a component of a video compression engine.

3. The method of claim 1 , wherein the block has a block width of a first number of pixels and a block height of a second number of pixels.

4. The method of claim 1 , wherein the at least one memory stripe of the memory stripes comprises an array in the memory that is accessible sequentially within the at least one memory stripe and wherein reading, from the at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block comprises:

reading sequentially, from the at least one of the memory stripes of the memory, the number of the compressed bits that correspond to the at least one block.

5. The method of claim 1 , further comprising:

determining a number of pixel stripes that correspond to the image based at least on the size of the image, the pixel stripes having pixel stripe widths of a number of pixels.

6. The method of claim 5 , further comprising:

allocating an encoder buffer to at least one of the pixel stripes; and

storing the compressed bits generated from pixels of at least one of the pixel stripes in the encoder buffer allocated for the at least one of the pixel stripes.

7. The method of claim 6 , wherein writing the compressed bits to the at least one of the memory stripes of the memory further comprises:

writing the compressed bits from the encoder buffer allocated for the at least one of the pixel stripes to the at least one of the memory stripes of the memory.

8. The method of claim 7 , further comprising:

allocating a decoder buffer to at least one of the memory stripes; and

storing, in the decoder buffer allocated to the at least one of the memory stripes, the number of the compressed bits read from the at least one of the memory stripes.

9. The method of claim 8 , wherein the decoding the number of the compressed bits to generate the at least one block comprises:

decoding the number of the compressed bits stored in the decoder buffer to generate the at least one block.

10. The method of claim 1 , wherein the at least one of the memory stripes comprises a data structure that contains a number of sequential rows having the memory stripe width.

11. The method of claim 10 , further comprising:

writing the compressed bits to the sequential rows of the at least one of the memory stripes of the memory; and

reading, from a number of the sequential rows of the at least one of the memory stripes of the memory, the number of the compressed bits that correspond to the at least one block in a single burst.

12. A device comprising:

a memory that is partitioned into a number of memory stripes having widths of a number of bits;

a raster to block encoder that is configured to:

receive image information associated with pixels of an image in raster order;

compress the image information associated with the pixels of the image in the raster order to generate compressed bits that correspond to at least one of memory stripes of the memory; and

write the compressed bits to the at least one of the memory stripes of the memory;

a raster to block decoder that is configured to:

read, from the at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block; and

decode the number of the compressed bits to generate the at least one block.

13. The device of claim 12 , wherein the memory comprises dynamic random-access memory.

14. The device of claim 12 , wherein the raster to block decoder is configured to provide the at least one block to a video compression engine.

15. The device of claim 12 , wherein the at least one of the memory stripes comprises an array in the memory that is accessible sequentially within the at least one memory stripes, the array comprising a number of sequential rows having the width of the number of bits.

16. The device of claim 15 , wherein:

the raster to block encoder is configured to write the compressed bits to the sequential rows of the at least one of the memory stripes of the memory; and

the raster to block decoder is configured to read, from a number of the sequential rows of the at least one of the memory stripes of the memory, the number of the compressed bits that correspond to the at least one block in a single burst.

17. The device of claim 12 , wherein the image information associated with the pixels of the image comprises luma values associated with the pixels of the image.

18. A computer program product comprising instructions stored in at least one tangible non-transitory computer-readable storage medium, the instructions comprising:

instructions for receiving pixels of an image in raster order;

instructions for compressing the pixels of the image in the raster order to generate compressed bits that correspond to at least one of a number of memory stripes in a memory, the at least one of the memory stripes having a width of a number of bits;

instructions for writing the compressed bits to the at least one of the memory stripes of the memory;

instructions for reading, from the at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block; and

instructions for decoding the number of the compressed bits to generate the at least one block.

19. The computer program product of claim 18 , wherein the instructions further comprise:

instructions for determining the number of memory stripes based at least on a size of the image.

20. The computer program product of claim 18 , wherein the instructions further comprise instructions for providing the at least one block to a video compression engine.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2014
From: MACINNIS, ALEXANDER GARLAND
To: BROADCOM CORPORATION
Reel/Frame 032110/0229 →