Memory system components that support error detection and correction
The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. Moreover, the memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.
1. A method of operating a memory device, the method comprising:
receiving a write memory access command that specifies a write access of data and a write access of error information associated with the data at a memory bank within the memory device;
receiving a base row address associated with the write memory access command; and
generating first and second row addresses based on the base row address;
wherein the write access of data accesses a first row in a first storage region of the memory bank based on the first row address; and
wherein the write access of error information accesses a second row in a second storage region of the memory bank based on the second row address.
2. The method of claim 1 , wherein the method further comprises writing the data to the first row in parallel with writing the error information associated with the data to the second row.
3. The method of claim 1 , wherein the number of storage cells in the first storage region is different than the number of storage cells in the second storage region.
4. The method of claim 3 , wherein the number of storage cells in the first storage region is 8 times the number of storage cells in the second storage region.
5. The method of claim 1 , wherein the method further comprises:
using a bit in the first row address to identify the first row to be either in a first subsection or a second subsection of the first storage region in order to access the first row; and
using a bit in the second row address to identify the second row to be either in a second subsection or a first subsection of the second storage region in order to access the second row.
6. The method of claim 5 , wherein:
if the first row is in the first subsection of the first storage region, the second row is in the second subsection of the second storage region; and
if the first row is in the second subsection of the first storage region, the second row is in the first subsection of the second storage region.
7. A memory device, comprising:
a memory bank;
circuitry to receive a write memory access command that specifies a write access of data and a write access of error information associated with the data at the memory bank;
circuitry to receive a base row address associated with the write memory access command; and
circuitry to generate first and second row addresses based on the base row address;
wherein the write access of data is to access a first row in a first storage region of the memory bank based on the first row address; and
wherein the write access of error information is to access a second row in a second storage region of the memory bank based on the second row address.
8. The memory device of claim 7 , wherein the first storage region and the second storage region are of different respective sizes.
9. The memory device of claim 7 , wherein:
a first row decoder is located between a first subsection and a second subsection of the first storage region; and
a second row decoder is located between a first subsection and a second subsection of the second storage region.
10. The memory device of claim 9 , wherein:
the first subsection of the first storage region and the first subsection of the second storage region share a first column decoder and a first column input/output (I/O) circuit; and
the second subsection of the first storage region and the second subsection of the second storage region share a second column decoder and a second column I/O circuit.
11. The memory device of claim 9 , wherein:
if the first row is in the first subsection of the first storage region, the second row is in the second subsection of the second storage region; and
if the first row is in the second subsection of the first storage region, the second row is in the first subsection of the second storage region.
12. The memory device of claim 7 , further comprising:
circuitry to use a bit in the first row address to identify the first row to be either in a first subsection or a second subsection of the first storage region in order to access the first row; and
circuitry to use a bit in the second row address to identify the second row to be either in a second subsection or a first subsection of the second storage region in order to access the second row.
13. The memory device of claim 7 , embodied as a dynamic random access memory (DRAM) device.
14. A memory device, comprising:
memory banks;
circuitry to receive a write memory access command that specifies a write access of data and a write access of error information associated with the data;
circuitry to receive a base row address associated with the write memory access command for a specified one of the memory banks; and
circuitry to generate first and second row addresses based on the base row address;
wherein the write access of data is to access a first row in a first storage region of the specified one of the memory banks based on the first row address; and
wherein the write access of error information is to access a second row in a second storage region of the specified one of the memory banks based on the second row address.
15. The memory device of claim 14 , wherein for each of the memory banks, the first storage region and the second storage region are of different respective sizes.
16. The memory device of claim 14 , wherein for each of the memory banks:
a first row decoder is located between a first subsection and a second subsection of the first storage region; and
a second row decoder is located between a first subsection and a second subsection of the second storage region.
17. The memory device of claim 16 , wherein for each of the memory banks:
the first subsection of the first storage region and the first subsection of the second storage region share a first column decoder and a first column input/output (I/O) circuit; and
the second subsection of the first storage region and the second subsection of the second storage region share a second column decoder and a second column I/O circuit.
18. The memory device of claim 16 , wherein for each one of the memory banks:
if the first row is in the first subsection of the first storage region of the one of the memory banks, the second row is in the second subsection of the second storage region of the one of the memory banks; and
if the first row is in the second subsection of the first storage region of the one of the memory banks, the second row is in the first subsection of the second storage region of the one of the memory banks.
19. The memory device of claim 14 , further comprising for each of the memory banks:
circuitry to use a bit in the first row address to identify the first row to be either in a first subsection or a second subsection of the first storage region in order to access the first row; and
circuitry to use a bit in the second row address to identify the second row to be either in a second subsection or a first subsection of the second storage region in order to access the second row.
20. The memory device of claim 14 , embodied as a dynamic random access memory (DRAM) device.