Methods and apparatus for testing and repairing digital memory circuits
An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.
1. A digital memory system, said digital memory system comprising:
a set of memory banks, each of said memory banks able to be accessed independent of the other memory banks in said set of memory banks, each of said memory banks comprising a plurality of memory rows; and
a memory testing system for testing said set of memory banks, said memory testing system comprising
a hunt pointer for pointing to a next memory bank to be tested, said memory testing system skipping said next memory bank when a memory access is currently blocking access said next memory bank;
a first deficit bank pointer for identifying a first deficit memory bank that has been skipped from a recent testing attempt due to a blocking memory access, and
a first deficit counter associated with said first deficit bank pointer, said first deficit counter for storing a count of times said first deficit memory bank has been skipped for testing;
wherein said first deficit memory bank identified in said first deficit bank pointer is given priority for testing over said next memory bank pointed to by said hunt pointer when said first deficit counter is not zero.
2. The digital memory system as set forth in claim 1 wherein said memory testing system further comprises a memory row pointer for each memory bank in said set of memory banks.
3. The digital memory system as set forth in claim 1 wherein said memory test system decrements said first deficit bank counter upon testing said first deficit memory bank identified by said first deficit bank pointer.
4. The digital memory system as set forth in claim 1 wherein said memory testing system increments said hunt pointer upon testing said next memory bank identified by said hunt pointer.
5. The digital memory system as set forth in claim 1 wherein said memory testing system further comprises
a second deficit bank pointer for identifying a second deficit memory bank that has been blocked from a recent testing attempt, and
a second deficit counter associated with said second deficit bank pointer, said second deficit counter for storing a count of times said second deficit memory bank has been skipped for testing;
wherein said first deficit memory bank identified in said first deficit bank pointer is given priority over said next memory bank pointed to by said hunt pointer when said first deficit counter is not zero and said second deficit memory bank identified in said second deficit bank pointer is given priority over said next memory bank pointed to by said hunt pointer when said second deficit counter is not zero.
6. The digital memory system as set forth in claim 5 wherein when both said first deficit counter and said second deficit counter are non zero, said memory testing system determines the greater value of said first deficit counter and said second deficit counter and then attempts to test a memory bank associated with the greater value.
7. The digital memory system as set forth in claim 5 wherein when both said first deficit counter and said second deficit counter are non zero, said memory testing system attempts to test either said first deficit memory bank identified by said first deficit bank pointer or said second deficit memory bank identified by said second deficit bank pointer on a round robin basis.
8. The digital memory system as set forth in claim 5 wherein when both said first deficit counter and said second deficit counter are non zero, said memory testing system randomly selects either said first deficit memory bank identified by said first deficit bank pointer or said second deficit memory bank identified by said second deficit bank pointer for testing.
9. The digital memory system as set forth in claim 5 wherein when both said first deficit counter and said second deficit counter are non zero, said memory testing system randomly selects either said first deficit memory bank identified by said first deficit bank pointer or said second deficit memory bank identified by said second deficit bank pointer depending on which was blocked earlier.
10. The digital memory system as set forth in claim 1 wherein said digital memory system comprises an embedded dynamic memory system.
11. A method of testing memory cells in a multi-bank dynamic memory system, said method of testing memory cells comprising:
testing memory banks in said multi-bank dynamic memory system in a nominal round-robin manner;
skipping a test of a first deficit memory bank when there is a conflict with a first memory access accessing said first deficit memory bank; and
immediately testing said first deficit memory bank when there is no longer a conflict with a memory access accessing said first deficit memory bank.
12. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 11 wherein a first deficit bank pointer is used to identify said first deficit memory bank skipped during a testing round.
13. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 12 wherein a first deficit counter is used to identify a number of number of testing cycles that have consecutively skipped said first deficit memory bank.
14. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 13 further comprising:
decrementing said first deficit counter upon testing said first deficit memory bank.
15. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 11 wherein a hunt pointer is used to identify a next memory bank to test.
16. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 15 further comprising
incrementing said hunt pointer after testing a next memory bank identified by said hunt pointer.
17. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 15 further comprising
skipping a test of a second deficit memory bank when there is a conflict with a second memory access accessing said second deficit memory bank; and
immediately testing said first deficit memory bank or second deficit memory bank when there is no longer a conflict with accessing said first deficit memory bank or said second deficit memory bank.
18. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 17 wherein said method tests said first deficit memory bank or second deficit memory bank depending on which has been skipped the greater number of times.
19. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 17 wherein said method tests said first deficit memory bank or second deficit memory bank on a random basis.
20. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 17 wherein said method tests said first deficit memory bank or second deficit memory bank on a round robin basis.
21. The method of testing memory cells in a multi-bank dynamic memory system as set forth in claim 17 wherein said method tests said first deficit memory bank or second deficit memory bank depending on which was skipped earlier.