IP Library Granted Patent US 9,190,007
Granted Patent B2
US 9,190,007 · App. 14/161,723 · Granted Nov 17, 2015

Display device

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Quick Facts
Patent No.
US 9,190,007
App. No.
14/161,723
Granted
Nov 17, 2015
Kind
B2
Abstract

A circuit block of a driving circuit of a display device includes a first transistor that has a gate being connected to a first node having an active potential during an output period, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line, a second transistor that has a gate being connected to a second node having an active potential during a non-output period, and controls electrical conduction between the first node and an inactive potential line, and a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line applied with a first period signal having an active potential at the time of termination of the output period.

Claims (15)

1. A display device comprising:

a plurality of scanning signal lines that are disposed side by side within a rectangular display region so as to be parallel to one side of the rectangle, and are applied with an active potential which is a potential for allowing electrical conduction of a pixel transistor; and

a driving circuit that sequentially applies the active potential from one ends of the plurality of scanning signal lines disposed side by side,

wherein the driving circuit has multiple stages of circuit blocks which are circuits applying an active potential to the plurality of scanning signal lines, and

wherein at least one stage of the circuit block in the multiple stages of circuit blocks includes

a first transistor that has a gate being connected to a first node having an active potential during an output period including a period in which the active potential is applied to the corresponding scanning signal line, and controls electrical conduction between a first clock signal line being applied with a first clock signal and the scanning signal line,

a second transistor that has a gate being connected to a second node having an active potential during a non-output period which is a period other than the output period, and controls electrical conduction between the first node and an inactive potential line fixed to an inactive potential, and

a third transistor that has a gate being connected to the first node, and controls electrical conduction between the second node and a first cyclic signal line that is applied with a first cyclic signal having an active potential at the time of termination of the output period and an inactive potential during the output period.

2. The display device according to claim 1 , wherein the first cyclic signal is a clock signal other than the first clock signal in multiphase clock signals including the first clock signal.

3. The display device according to claim 1 , wherein the first cyclic signal is an output to the scanning signal line of the circuit block of another stage.

4. The display device according to claim 1 , wherein the first cyclic signal line is connected to the third transistor through diode connection.

5. The display device according to claim 1 ,

wherein the driving circuit is a bidirectional driving circuit that sequentially applies the active potential in one direction selected from a forward direction from the one ends of the plurality of scanning signal lines and a backward direction from the other ends thereof, and

wherein the circuit block further includes a fourth transistor that has a gate being connected to the first node and controls electrical conduction between the second node and a second cyclic signal line applied with a second cyclic signal having an active potential at the time of termination of an output period in a reverse direction.

6. The display device according to claim 5 , wherein the second cyclic signal is the same signal as the first cyclic signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2014
From: MIYAMOTO, MOTOHARU; OCHIAI, TAKAHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 032024/0728 →