Test access port and TMS communication circuitry with state machines
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
1. An integrated circuit comprising:
A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;
B. test access port circuitry coupled to the test data in lead, the test data out lead, the test clock lead, and the test mode select lead, the test access port circuitry including a data register coupled to the test data in lead and the test data out lead and having parallel connections with other circuitry, and including state machine circuitry coupled with the test clock lead, the test mode select lead, and the data register; and
C. TMS communication circuitry having a bi-directional data connection with the test mode select lead and connections with data source circuitry and data destination circuitry that are separate from the other circuitry, the TMS communication circuitry including state machine circuitry, separate from the state machine in the test access port circuitry, coupled with the data source circuitry and the data destination circuitry.
2. The integrated circuit of claim 1 in which the data destination circuitry includes any one of an address bus, a data bus, a Ram memory, a Cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, and a bus coupled to circuitry external to the IC.
3. The integrated circuit of claim 1 in which the data source circuitry includes any one of an address bus, a data bus, a Ram memory, a Cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, and a bus coupled to circuitry external to the IC.
4. The integrated circuit of claim 1 in which the TMS communication circuitry includes data input circuitry that includes a serial input parallel output register.
5. The integrated circuit of claim 1 in which the TMS communication circuitry includes data output circuitry that includes a parallel input serial output register.
6. The integrated circuit of claim 1 in which the data destination circuitry is separate from the data source circuitry.