Data parallel computing on multiple processors
A method and an apparatus that allocate one or more physical compute devices such as central processing units or graphical processing units attached to a host processing unit running an application for executing one or more threads of the application are described. The allocation may be based on data representing a processing capability requirement from the application for executing an executable in the one or more threads. A compute device identifier may be associated with the allocated physical compute devices to schedule and execute the executable in the one or more threads concurrently in one or more of the allocated physical compute devices concurrently.
1. A computer implemented method comprising:
receiving, from a host application executing on a host processor, a request to identify any compute device that matches a processing requirement for a task corresponding to source code in the host application;
sending, to the host application, a compute identifier for each compute device that matches the processing requirement;
receiving, from the host application, a request specifying a compute identifier selected by the host application; and
generating, by the host processor, a context for the compute device that corresponds to the selected compute identifier and defines an execution queue for the selected compute device.
2. The computer implemented method of claim 1 further comprising:
generating, by the host processor, a compute identifier for each compute device that matches the processing requirement.
3. The computer implemented method of claim 1 further comprising:
retrieving, by the host processor, characteristics of each compute device coupled to the host processor.
4. The computer implemented method of claim 1 , wherein generating the context further comprises allocating resources for the selected compute device.
5. The computer implemented method of claim 1 , wherein the processing requirement specifies multiple physical processors.
6. The computer implemented method of claim 5 further comprising:
defining, by the host processor, a set of physical processors as a logical compute device; and
generating, by the host processor, a compute identifier for the logical compute device.
7. The computer implemented method of claim 1 , wherein the requests from the host application are processed by an interpreter during execution of the host application.
8. A non-transitory computer readable storage medium storing instruction that when executed by a host processor cause the host processor to perform operations comprising:
receiving, from a host application executing on the host processor, a request to identify any compute device that matches a processing requirement for a task corresponding to source code in the host application;
sending, to the host application, a compute identifier for each compute device that matches the processing requirement;
receiving, from the host application, a request specifying a compute identifier selected by the host application; and
generating, by the host processor, a context for the compute device that corresponds to the selected compute identifier and defines an execution queue for the selected compute device.
9. The non-transitory computer readable storage medium of claim 8 wherein the instructions further cause the host processor to perform an operation comprising:
generating a compute identifier for each compute device that matches the processing requirement.
10. The non-transitory computer readable storage medium of claim 8 wherein the instructions further cause the host processor to perform an operation comprising:
retrieving characteristics of each compute device coupled to the host processor.
11. The non-transitory computer readable storage medium of claim 8 , wherein generating the context further comprises allocating resources for the selected compute device.
12. The non-transitory computer readable storage medium of claim 8 , wherein the processing requirement specifies multiple physical processors.
13. The non-transitory computer readable storage medium of claim 12 , wherein the instructions further cause the host processor to perform operations comprising:
defining a set of physical processors as a logical compute device; and
generating a compute identifier for the logical compute device.
14. The non-transitory computer readable storage medium of claim 8 , wherein the requests from the host application are processed by an interpreter during execution of the host application.
15. A system comprising:
a host processor coupled to a memory through a bus;
a plurality of compute devices coupled to the host processor through a bus; and
a platform layer process stored as instructions in the memory to cause the host processor to
receive, from a host application executing on the host processor, a request to identify any compute device that matches a processing requirement for a task corresponding to source code in the host application;
send, to the host application, a compute identifier for each compute device that matches the processing requirement;
receive, from the host application, a request specifying a compute identifier selected by the host application; and
generate, by the host processor, a context for the compute device that corresponds to the selected compute identifier and defines an execution queue for the selected compute device.
16. The system of claim 15 wherein the instructions further cause the host processor to generate a compute identifier for each compute device that matches the processing requirement.
17. The system of claim 15 wherein the instructions further cause the host processor to retrieve characteristics of each compute device coupled to the host processor.
18. The system of claim 15 , wherein generating the context further comprises allocating resources for the selected compute device.
19. The system of claim 15 , wherein the processing requirement specifies multiple physical processors.
20. The system of claim 19 , wherein the instructions further cause the host processor to define a set of physical processors as a logical compute device and to generate a compute identifier for the logical compute device.
21. The system of claim 15 further comprising an interpreter process stored as instructions in the memory to cause the host processor to interpret the requests from the host application during execution of the host application.