Proposed is a bias circuit for a transistor in a C class amplifier. The bias circuit comprises: a class AB amplifier bias voltage generating means adapted to generate a bias voltage at an output terminal; and a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch. Closure of the switch connects the second reference voltage to the control terminal of the transistor to cause a shift in the bias voltage generated by the class AB amplifier bias voltage generating means to achieve a predetermined class C bias voltage at the output terminal.
1. A bias circuit for a transistor in a C class amplifier, the bias circuit comprising:
a class AB amplifier bias voltage generating means adapted to generate a bias voltage at an output terminal; and
a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch,
wherein closure of the switch connects the second reference voltage to the control terminal of the transistor to cause a shift in the bias voltage generated by the class AB amplifier bias voltage generating means to achieve a predetermined class C bias voltage at the output terminal.
2. The bias circuit of claim 1 , wherein a first resistor is connected between the control terminal of the transistor and the switch, and a second resistor is connected between the control terminal of the transistor and the output terminal.
3. The bias circuit of claim 1 , wherein the class AB amplifier bias voltage generating means comprise a current mirror circuit.
4. The bias circuit of claim 3 , wherein the current mirror circuit comprises first and second MOS transistors provided in a looped arrangement, wherein the drain of the first MOS transistor is connected to a current source IREF, wherein a voltage source is connected to the drain of the second MOS transistor, and wherein the gate of the second MOS transistor is connected to the drain of the first MOS transistor, such that the source of the second MOS transistor provides the bias voltage.
5. The bias circuit of claim 1 , wherein the bias circuit is an integrated circuit.
6. The bias circuit of claim 5 , wherein the bias circuit is integrated on the same circuit as the transistor to be biased.
7. The bias circuit of claim 5 , wherein the second reference voltage (Vctrl) is provided externally to the bias circuit.
8. The bias circuit of claim 1 , wherein the first reference voltage is a ground voltage.
9. A Doherty amplifier bias circuit comprising a bias circuit according to claim 1 .
10. A radio frequency amplifier circuit comprising a bias circuit according to claim 1 .
11. A method of biasing a transistor in a C class amplifier, using a bias circuit comprising: a class AB amplifier bias voltage generating means; and a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch, the method comprising the steps of:
generating a bias voltage at an output terminal of the bias circuit using the class AB amplifier bias voltage generating means; and
activating the switch to connect the second reference voltage to the control terminal of the transistor so as to cause a shift in the bias voltage generated by the class AB amplifier bias voltage generating means to achieve a predetermined class C bias voltage at the output terminal.
12. A computer program product comprising a computer-readable storage medium having a computer readable-program code configured to perform the steps of claim 11 when executed on a processor for biasing a transistor in a C class amplifier using a bias circuit comprising: a class AB amplifier bias voltage generating means; and a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch.