IP Library Granted Patent US 9,070,713
Granted Patent B2
US 9,070,713 · App. 14/165,187 · Granted Jun 30, 2015

Power semiconductor device and methods for fabricating the same

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Quick Facts
Patent No.
US 9,070,713
App. No.
14/165,187
Granted
Jun 30, 2015
Kind
B2
Abstract

A power semiconductor device includes: a drain region of a first conductive type; a drift region of a first conductive type formed on the drain region; a first body region of a second conductive type formed below an upper surface of the drift region; a second body region of a second conductive type formed below the upper surface of the drift region and in the first body region; a third body region of a second conductive type formed by protruding downwards from a lower end of the first body region; a source region of a first conductive type formed below the upper surface of the drift region and in the first body region; and a gate insulating layer formed on channel regions of the first body region and on the drift region between the first body regions.

Claims (13)

1. A method of fabricating a power semiconductor device, the method comprising:

forming a drain region of a first conductive type;

forming a drift region of the first conductive type on the drain region;

forming a first body region of a second conductive type below an upper surface of the drift region;

forming a second body region of the second conductive type having a depth shallower than a depth of the first body region below the upper surface of the drift region and in the first body region;

forming a third body region of the second conductive type protruded downwards from a lower end of the first body region to a position shallower than that of an upper surface of the drain region;

forming a source region of the first conductive type having a depth shallower than the depth of the second body region below the upper surface of the drift region and in the first body region;

forming a gate insulating layer on a channel region of the first body region and on the drift region;

forming a gate electrode on the gate insulating layer;

forming a source electrode electrically connected to the source region; and

forming a drain electrode electrically connected to the drain region.

2. The method of claim 1 , wherein the first body region has a doping concentration of the second conductive type lower than that of the second body region, and the third body region has a doping concentration of the second conductive type lower than that of the second body region.

3. The method of claim 1 , wherein the forming of the first body region is performed after performing the forming of the third body region and the forming of the second body region is performed after performing the forming of the first body region.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →