Method for improving the accuracy of an exponential current digital-to-analog (IDAC) using a binary-weighted MSB
A method for the design synthesis of an exponential current digital-to-analog (IDAC) using a binary-weighted MSB. The design synthesis involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) comprising (1) defining a differential non-linearity (DNL); (2) defining number of LSB bits needed for the targeted DNL with a binary weighted MSB; (3) calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base; (4) deriving the minimum current for the Imax; (5) defining the LSB as an exponential current mirror according to the specified relationship for the ILSB; and (6) defining a binary-weighted MSB according to the specified relationship for IMSB.
1. A method to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) comprising:
defining a differential non-linearity (DNL);
defining number of LSB bits needed for the targeted DNL with a binary weighted MSB;
calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base;
deriving the minimum current for the Imax;
defining the LSB as an exponential current mirror according to the specified relationship for the ILSB;
defining a binary weighted MSB according to the specified relationship for IMSB; and
defining a differential non-linearity (DNL) according to the definition
DNL
=
1
+
DNL
%
100
.
2. The method of claim 1 , wherein said definition of LSB bits needed for the targeted DNL with binary-weighted MSB is according to the definition
DNL MSB =(DNL) 2 nLSB .
3. The method of claim 1 , wherein said calculation of the number of bits to be used for the binary-weighted MSB to get the desired IDAC base, is according to the definition
base
=
(
2
)
2
nMSB
DNL
.
4. The method of claim 1 , wherein said derivation of the minimum current for the Imax is according to the definition,
Io=I max/base.
5. The method of claim 1 , wherein said definition of the LSB as an exponential current mirror according to the specified relationship for the ILSB,
ILSB
=
I
0
G
*
(
DNL
)
LSB
code
For
LSB
code
=
0
,
…
nLSB
.
6. The method of claim 1 , wherein said value of a nMSB for a binary weighted MSB of at least 2 bits.
7. The method of claim 1 , wherein said value of an nMSB for a binary weighted MSB of 3 bits.
8. A method of design synthesis to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a LSB exponential IDAC and an binary-weighted most significant bit (MSB) exponential IDAC whose method of design synthesis comprising:
defining a differential non-linearity (DNL);
defining number of LSB bits needed for the targeted DNL with a binary weighted MSB;
calculating the number of bits to be used for the binary-weighted MSB to get the desired IDAC base;
deriving the minimum current for the Imax;
defining the LSB as an exponential current mirror according to the specified relationship for the ILSB;
defining a binary weighted MSB according to the specified relationship for IMSB;
synthesizing said LSB exponential IDAC;
synthesizing said binary-weighted most significant bit (MSB) exponential IDAC;
integrating said LSB exponential IDAC and said binary-weighted most significant bit (MSB) exponential IDAC;
optimize said exponential current digital-to-analog converter (IDAC); and
synthesizing said exponential current digital-to-analog converter (IDAC).
9. The method of design synthesis of claim 8 , to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a LSB exponential IDAC and an binary-weighted most significant bit (MSB) exponential IDAC whose method of design synthesis providing a means for removal of MSB bits for reduced complexity.
10. The method of design synthesis of claim 8 , to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a LSB exponential IDAC and an binary-weighted most significant bit (MSB) exponential IDAC whose method of design synthesis providing a means for reduction of MSB bits for improved matching.
11. The method of design synthesis of claim 8 , to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using a LSB exponential IDAC and an binary-weighted most significant bit (MSB) exponential IDAC whose method of design synthesis providing a means for reduction of MSB bits for reduced area and size.
12. The method of design synthesis of claim 8 , to achieve an exponential current digital-to-analog converter (IDAC) having improved accuracy using said LSB exponential IDAC and said binary-weighted most significant bit (MSB) exponential IDAC whose method is defined by forming two exponential current mirror networks, where at least one of the current source networks is for the least significant bit (LSB), and at least one of the second current source networks is for the most significant bit (MSB).