Adaptively controlled digital pre-distortion in an RF power amplifier using an integrated signal analyzer with enhanced analog-to-digital conversion

1. A pre-distortion circuit for a power amplifier, comprising:

a digital interface for receiving a complex-value digital baseband signal;

a mixed-signal pre-distortion circuit adaptively controlled by a set of parameter values, receiving the complex-value digital baseband signal to provide a pre-distorted signal for input to the power amplifier, the mixed-signal pre-distortion circuit comprises:

a digital pre-distortion circuit that transforms the complex-value digital baseband signal to a pre-distorted complex-value digital baseband signal by applying to the complex-value digital baseband signal a memory-less non-linear gain and a polynomial function based on the complex-value digital baseband signal and one or more delayed copies of the complex-value digital baseband signal;

an up-converter that converts the pre-distorted complex-value digital baseband signal to the pre-distorted signal; and

an over-sampler that increases a data rate in the complex-value digital baseband signal by at least a factor of 2; and

a signal analyzer receiving an output signal from the power amplifier to provide the parameter values from time to time to the mixed-signal pre-distortion circuit.

2. The pre-distortion circuit of claim 1 , wherein the polynomial function comprises one or more powers of a moduli of the complex-value digital baseband signal and one or more powers of a moduli of the delayed copies of the complex-value digital baseband signal.

3. The pre-distortion circuit of claim 2 , wherein the memory-less non-linear gain is applied after a unit delay to the complex-value digital baseband signal.

4. The pre-distortion circuit of claim 1 , wherein the memory-less non-linear gain is a polynomial function of the complex-value digital baseband signal.

5. The pre-distortion circuit of claim 1 , wherein the digital pre-distortion circuit uses look-up tables to compute either one or both of the memory-less non-linear gain and the polynomial function.

6. The pre-distortion circuit of claim 1 , wherein the digital pre-distortion circuit comprises a digital signal processor.

7. The pre-distortion circuit of claim 1 , wherein the signal analyzer comprises:

a quadrature down-converter that converts the output signal from the power amplifier to a complex-value feedback signal that is at baseband or at a near-baseband intermediate frequency;

an analog-to-digital converter that converts the complex-value feedback signal to a first digital complex-value feedback signal; and

a digital signal analysis circuit that receives the first digital complex-value feedback signal to provide the parameter values.

8. The pre-distortion circuit of claim 7 , wherein the up-converter and the quadrature down-converter operate from a common timing signal.

9. The pre-distortion circuit of claim 7 , wherein the signal analyzer receives in addition the pre-distorted signal, the signal analyzer further comprises:

a second quadrature down-converter that converts the pre-distorted signal to a second complex-value feedback signal that is at baseband or at the near-baseband intermediate frequency; and

a second analog-to-digital converter that converts the second complex-value feedback signal to a second digital complex-value feedback signal; and

wherein the digital signal analysis circuit provides the parameter values based on both the first digital complex-value feedback signal and the second digital complex-value feedback signal.

10. The pre-distortion circuit of claim 9 , wherein the digital signal analysis circuit performs one or more of DC offset correction, I/Q imbalance correction and delay matching on either or both of the first digital complex-value feedback signal and the second digital complex-value feedback signal.

11. The pre-distortion circuit of claim 9 , wherein the digital signal analysis performs linear distortion correction on the first complex-value feedback signal.

12. The pre-distortion circuit of claim 9 , wherein the digital signal analysis circuit computes the parameter values based on minimizing a difference between the first complex-value feedback signal and the second complex-value feedback signal.

13. The pre-distortion circuit of claim 7 , wherein the memory-less non-linear gain is computed based on a magnitude of the first digital complex-value feedback signal.

14. The pre-distortion circuit of claim 7 , wherein the signal analysis circuit comprises a digital signal processor.

15. The pre-distortion circuit of claim 1 , further comprising a crest-factor reduction circuit that reduces a crest factor in the complex-value digital baseband signal provided to the mixed-signal pre-distortion circuit.

16. The pre-distortion circuit of claim 1 , wherein the signal analyzer receives also a complex-value feed-forward signal representative of the complex-value digital baseband signal.

17. The pre-distortion circuit of claim 16 , further comprising a crest-factor reduction circuit that reduces a crest factor in the complex-value digital baseband signal, wherein the crest-factor reduction circuit provides the complex-value feed-forward signal.

18. The pre-distortion circuit of claim 16 , wherein the signal analyzer comprises:

a quadrature down-converter that converts the output signal from the power amplifier to a complex-value feedback signal that is at baseband or at a near-baseband intermediate frequency;

an analog-to-digital converter that converts the complex-value feedback signal to a first digital complex-value feedback signal; and

a digital signal analysis circuit that receives the first digital complex-value feedback signal to provide the parameter values.

19. The pre-distortion circuit of claim 18 , wherein the up-converter and the quadrature down-converter operate from a common timing signal.

20. The pre-distortion circuit of claim 18 , wherein the digital signal analysis circuit provides the parameter values based on both the first digital complex-value feedback signal and the complex-value feed-forward signal.

21. The pre-distortion circuit of claim 18 , wherein the digital signal analysis circuit performs one or more of DC offset correction, I/Q imbalance correction and delay matching on the first digital complex-value feedback signal and the complex-value feed-forward signal.

22. The pre-distortion circuit of claim 18 , wherein the digital signal analysis circuit performs one or more of I/Q imbalance correction, delay matching, complex gain adjustments, frequency offset correction and DC offset correction on the complex-value feed-forward signal.

23. The pre-distortion circuit of claim 18 , wherein the digital signal analysis circuit computes the parameter values based on minimizing a difference between the first complex-value feedback signal and the complex-value feed-forward signal.

24. The pre-distortion circuit of claim 18 , wherein the digital signal analysis performs frequency offset correction on the complex-value feed-forward signal.

25. The pre-distortion circuit of claim 18 , further comprising an analog-to-digital converter enhancer circuit that receives from the digital signal analysis circuit a data signal representing one or more clock periods of the complex value feed-forward signal.

26. The pre-distortion circuit of claim 25 , wherein the analog-to-digital converter enhancer circuit applies a current-steering digital-to-analog technique.

27. The pre-distortion circuit of claim 26 , wherein the analog-to-digital converter enhancer circuit comprises:

a digital-to-analog circuit that converts the data signal to a complex data current; and

a current combination circuit that provides an output current representative of a difference between the complex data current and the complex-value feedback signal.

28. The pre-distortion circuit of claim 27 , wherein the analog-to-digital converter enhancer circuit further comprises a resistor element that converts the output current into an output voltage.

29. The pre-distortion circuit of claim 28 , wherein the analog-to-digital converter enhancer circuit further comprises a second stage that receives the output voltage and a second data signal from the digital signal analysis circuit, the second stage applies a charge-redistribution technique.

30. The pre-distortion circuit of claim 29 , wherein the second stage comprises:

cascaded first and second tracking-and-hold circuits operated by complementary clock signals to provide a held voltage signal;

a digital-to-analog converter that converts to a second data signal to provide a voltage data signal; and

a voltage summer that provides a second-stage output signal representative of a voltage difference between the held voltage signal and the voltage data signal.

31. The pre-distortion circuit of claim 1 , wherein the mixed-signal pre-distortion circuit is integrated into a transceiver integrated circuit.

32. The pre-distortion circuit of claim 31 , wherein the signal analyzer is integrated into an integrated circuit separate from the transceiver integrated circuit.

33. The pre-distortion circuit of claim 1 , wherein the digital pre-distortion circuit and the signal analyzer are integrated into a mixed-signal integrated circuit.

34. The pre-distortion circuit of claim 33 , wherein the up-converter is integrated into an integrated circuit separate from the mixed-signal integrated circuit.

35. A pre-distortion circuit for a power amplifier, comprising:

a digital interface for receiving a complex-value digital baseband signal;

a mixed-signal pre-distortion circuit adaptively controlled by a set of parameter values, receiving the complex-value digital baseband signal to provide a pre-distorted signal for input to the power amplifier, the mixed-signal pre-distortion circuit comprises:

a digital pre-distortion circuit that transforms the complex-value digital baseband signal to a pre-distorted complex-value digital baseband signal by applying to the complex-value digital baseband signal a memory-less non-linear gain and a polynomial function based on the complex-value digital baseband signal and one or more delayed copies of the complex-value digital baseband signal,

wherein the polynomial function comprises one or more powers of a moduli of the complex-value digital baseband signal and one or more powers of a moduli of the delayed copies of the complex-value digital baseband signal; and

an up-converter that converts the pre-distorted complex-value digital baseband signal to the pre-distorted signal; and

a signal analyzer receiving an output signal from the power amplifier to provide the parameter values from time to time to the mixed-signal pre-distortion circuit.

36. A pre-distortion circuit for a power amplifier, comprising:

a digital interface for receiving a complex-value digital baseband signal;

a mixed-signal pre-distortion circuit adaptively controlled by a set of parameter values, receiving the complex-value digital baseband signal to provide a pre-distorted signal for input to the power amplifier, the mixed-signal pre-distortion circuit comprises:

a digital pre-distortion circuit that transforms the complex-value digital baseband signal to a pre-distorted complex-value digital baseband signal by applying to the complex-value digital baseband signal a memory-less non-linear gain and a polynomial function based on the complex-value digital baseband signal and one or more delayed copies of the complex-value digital baseband signal; and

an up-converter that converts the pre-distorted complex-value digital baseband signal to the pre-distorted signal;

a crest-factor reduction circuit that reduces a crest factor in the complex-value digital baseband signal provided to the mixed-signal pre-distortion circuit; and

a signal analyzer receiving an output signal from the power amplifier to provide the parameter values from time to time to the mixed-signal pre-distortion circuit.