A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
1. An integrated circuit (“IC”) comprising:
N sets of configurable circuits for jointly processing a set of data signals at a first data rate, wherein each set of configurable circuits processes the set of data signals at a second data rate that is a fraction of the first data rate, wherein each set of the configurable circuits reconfigure at each reconfiguration clock cycle, and wherein the N sets of configurable circuits comprise respective rescaled portions configured at different clock phases; and
a set of configuration data storage for iteratively supplying one of M sets of configuration data at each reconfiguration clock cycle to each set of configurable circuits.
2. The IC of claim 1 , wherein the first data rate is N times the second data rate.
3. The IC of claim 1 , wherein a first set of configurable circuits in the N sets of configurable circuits comprises combinational nodes and sequential nodes that are logically equivalent to combinational nodes and sequential nodes in a second set of configurable circuits in the N sets of configurable circuits.
4. The IC of claim 3 , wherein a plurality of the combinational nodes and sequential nodes in the first and second sets of configurable circuits are implemented by configurable logic circuits and configurable interconnect circuits configured by the set of configuration data stored in the configuration data storage.
5. The IC of claim 1 , wherein the N sets of configurable circuits are implementing a user defined design, wherein the user defined design specifies a user defined clock, wherein the first data rate corresponds to the N sets of configurable circuits jointly processing the set of data signals once every cycle of the user defined clock.
6. The IC of claim 5 , wherein the configurable circuits reconfigure M times in each cycle of the user defined clock.
7. The IC of claim 5 , wherein the reconfiguration clock is M/N times the user defined clock.
8. The IC of claim 5 , wherein the second data rate corresponds to one set of configurable circuits of the N sets of configurable circuits processing the set of data signals once every cycle of the user defined clock.
9. An integrated circuit (“IC”) comprising:
a set of configurable circuits for implementing a user defined module that processes a set of data signals at a first data rate, the set of configurable circuits configured to perform N replicas of the user defined module in parallel, each replica of the user defined module processing the set of data signals at a second data rate that is 1/N of the first data rate, wherein the set of the configurable circuits reconfigures at each reconfiguration clock cycle; and
a set of configuration data storage for iteratively supplying one of M sets of configuration data at each reconfiguration clock cycle to each set of configuration circuits, wherein each of the M sets of configuration data contains configuration data associated with different respective clock phases.
10. The IC of claim 9 , wherein a first replica of the user defined module comprises combinational nodes and sequential nodes that are logically equivalent to combinational nodes and sequential nodes in a second replica of the user defined module.
11. The IC of claim 10 , wherein a plurality of the combination nodes and sequential nodes in the first and second sets of configurable circuits are implemented by configurable logic circuits and configurable configured by the set of configuration data stored in the configuration data storage.
12. The IC of claim 9 , wherein the user defined module is a part of a user design that specifies a user defined clock, wherein the first data rate corresponds to the user defined module processing the set of data signals once every cycle of the user defined clock.
13. The IC of claim 12 , wherein the configurable circuits reconfigure M times in each cycle of the user defined clock.
14. The IC of claim 12 , wherein the reconfiguration clock rate is M/N times the user defined clock.
15. The IC of claim 12 , wherein the second data rate corresponds to one replica of the user defined module processing the set of data signals once every cycle of the user defined clock.
16. An electronic device, comprising:
an integrated circuit (“IC”) comprising:
a set of configurable logic circuits for implementing a user defined module that processes a set of data signals at a first rate, the set of configurable logic circuits configured to perform N replicas of the user defined module in parallel, each replica of the user defined module processing the set of data signals at a second data rate that is a fraction of the first data rate, wherein the set of configurable logic circuits reconfigures at each reconfiguration clock cycle; and
a set of configuration data storage for iteratively supplying one of M sets of configuration data at each reconfiguration clock cycle to each set of configurable logic circuits; and
a memory device for providing configuration data to the IC.
17. The IC of claim 16 , wherein the user defined module is part of a user design that specifies a user defined clock, wherein the first data rate corresponds to the user defined module processing the set of data signals once every cycle of the user defined clock.
18. The IC of claim 17 , wherein the reconfiguration clock rate is M/N times the user defined clock.
19. The IC of claim 17 , wherein the second data rate corresponds to one replica of the user designed module processing the set of data signals once every cycle of the user defined clock.